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| 80960HA/hd/ht 32-bit high-performance superscalar processor data sheet advance information product features n 32-bit parallel architecture load/store architecture sixteen 32-bit global registers sixteen 32-bit local registers 1.28 gbyte internal bandwidth (80 mhz) on-chip register cache n processor core clock 80960HA is 1x bus clock 80960hd is 2x bus clock 80960ht is 3x bus clock n binary compatible with other 80960 processors n issue up to 150 million instructions per second n high-performance on-chip storage 16 kbyte four-way set-associative instruction cache 8 kbyte four-way set-associative data cache 2 kbyte general purpose ram separate 128-bit internal paths for instructions/data n 3.3 v supply voltage 5 v tolerant inputs ttl compatible outputs n guarded memory unit provides memory protection user/supervisor read/write/execute n 32-bit demultiplexed burst bus per-byte parity generation/checking address pipelining option fully programmable wait state generator supports 8-, 16- or 32-bit bus widths 160 mbyte/s external bandwidth (40 mhz) n high-speed interrupt controller up to 240 external interrupts 31 fully programmable priorities separate, non-maskable interrupt pin n dual on-chip 32-bit timers auto reload capability and one-shot clkin prescaling, 1, 2, 4 or 8 jtag support - ieee 1149.1 compliant order number: 272495-007 july, 1998 notice: this document contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
80960HA/hd/ht advance information datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellec tual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties rel ating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products a re not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 80960HA/hd/ht may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1998 *third-party brands and names are the property of their respective owners. advance information datasheet iii 80960HA/hd/ht contents 1.0 about this document .............................................................................................. 1 2.0 intels 80960hx processor ...................................................................................... 1 2.1 the i960? processor family ................................................................................. 2 2.2 key 80960hx features.......................................................................................... 2 2.2.1 execution architecture ............................................................................. 2 2.2.2 pipelined, burst bus ................................................................................. 2 2.2.3 on-chip caches and data ram .............................................................. 3 2.2.4 priority interrupt controller ....................................................................... 3 2.2.5 guarded memory unit .............................................................................. 3 2.2.6 dual programmable timers ..................................................................... 4 2.2.7 processor self test .................................................................................. 4 2.3 instruction set summary ....................................................................................... 5 3.0 package information ................................................................................................. 6 3.1 pin descriptions .................................................................................................... 7 3.2 80960hx mechanical data ..................................................................................12 3.2.1 80960hx pga pinout .............................................................................12 3.2.2 80960hx pq4 pinout..............................................................................18 3.3 package thermal specifications .........................................................................23 3.4 heat sink adhesives ...........................................................................................26 3.5 powerquad4 plastic package.............................................................................26 3.6 stepping register information.............................................................................26 3.7 sources for accessories......................................................................................28 4.0 electrical specifications ........................................................................................29 4.1 absolute maximum ratings.................................................................................29 4.2 operating conditions...........................................................................................29 4.3 recommended connections ...............................................................................30 4.4 vcc5 pin requirements (v diff ) .........................................................................30 4.5 vccpll pin requirements.................................................................................31 4.6 dc specifications ................................................................................................32 4.7 ac specifications ................................................................................................34 4.7.1 ac test conditions ................................................................................37 4.8 ac timing waveforms ........................................................................................38 5.0 bus waveforms .........................................................................................................46 5.1 80960hx boundary scan chain ..........................................................................76 5.2 boundary scan description language example.................................................80 80960HA/hd/ht iv advance information datasheet figures 1 80960hx block diagram .......................................................................................1 2 80960hx 168-pin pga pinout view from top (pins facing down) ...............12 3 80960hx 168-pin pga pinout view from bottom (pins facing up) ...............13 4 80960hx 208-pin pq4 pinout .............................................................................18 5 measuring 80960hx pga case temperature ....................................................23 6 80960hx device identification register ..............................................................26 7 vcc5 current-limiting resistor ..........................................................................30 8 ac test load ......................................................................................................37 9 clkin waveform ................................................................................................38 10 output delay waveform......................................................................................38 11 output delay waveform......................................................................................38 12 output float waveform .......................................................................................39 13 input setup and hold waveform .........................................................................39 14 nmi ,xint7:0 input setup and hold waveform ..................................................39 15 hold acknowledge timings .................................................................................40 16 bus backoff (boff ) timings ..............................................................................40 17 tck waveform....................................................................................................41 18 input setup and hold waveforms for t bsis1 and t bsih1 ....................................41 19 output delay and output float for t bsov1 and t bsof1 ......................................42 20 output delay and output float waveform for t bsov2 and t bsof2 ....................42 21 input setup and hold waveform for t bsis2 and t bsih2 ......................................42 22 rise and fall time derating at 85c and minimum v cc ....................................43 23 i cc active (power supply) vs. frequency ...........................................................43 24 i cc active (thermal) vs. frequency ....................................................................44 25 output delay or hold vs. load capacitance .......................................................44 26 output delay vs. temperature ............................................................................45 27 output hold times vs. temperature ...................................................................45 28 output delay vs. v cc ..........................................................................................45 29 cold reset waveform .........................................................................................46 30 warm reset waveform .......................................................................................47 31 entering once mode .........................................................................................48 32 non-burst, non-pipelined requests without wait states ...................................49 33 non-burst, non-pipelined read request with wait states.................................50 34 non-burst, non-pipelined write request with wait states .................................51 35 burst, non-pipelined read request without wait states, 32-bit bus .................52 36 burst, non-pipelined read request with wait states, 32-bit bus ......................53 37 burst, non-pipelined write request without wait states, 32-bit bus .................54 38 burst, non-pipelined write request with wait states, 32-bit bus ......................55 39 burst, non-pipelined read request with wait states, 16-bit bus ......................56 40 burst, non-pipelined read request with wait states, 8-bit bus ........................57 41 non-burst, pipelined read request without wait states, 32-bit bus .................58 42 non-burst, pipelined read request with wait states, 32-bit bus ......................59 43 burst, pipelined read request without wait states, 32-bit bus.........................60 44 burst, pipelined read request with wait states, 32-bit bus..............................61 45 burst, pipelined read request with wait states, 8-bit bus................................62 46 burst, pipelined read request with wait states, 16-bit bus..............................63 47 using external ready ........................................................................................64 48 terminating a burst with bterm ........................................................................65 49 breq and bstall operation ............................................................................66 advance information datasheet v 80960HA/hd/ht 50 boff functional timing. boff occurs during a burst or non-burst data cycle. .......................................................................................... 67 51 hold functional timing .................................................................................... 68 52 lock delays holda timing ............................................................................ 69 53 fail functional timing....................................................................................... 69 54 a summary of aligned and unaligned transfers for 32-bit regions ................. 70 56 a summary of aligned and unaligned transfers for 16-bit bus ........................ 72 57 a summary of aligned and unaligned transfers for 8-bit bus .......................... 73 58 idle bus operation.............................................................................................. 74 59 bus states .......................................................................................................... 75 tables 1 80960hx product description................................................................................ 1 2 fail codes for bist (bit 7 = 1) ............................................................................. 4 3 remaining fail codes (bit 7 = 0)........................................................................... 4 4 80960hx instruction set ........................................................................................ 5 5 80960HA/hd/ht package types and speeds ..................................................... 6 6 pin description nomenclature............................................................................... 7 7 80960hx processor family pin descriptions ........................................................ 8 8 80960hx 168-pin pga pinout signal name order ........................................14 9 80960hx 168-pin pga pinout pin number order ..........................................16 10 80960hx pq4 pinout signal name order ......................................................19 11 80960hx pq4 pinout pin number order........................................................21 12 maximum t a at various airflows in c (pga package only)..............................24 13 80960hx 168-pin pga package thermal characteristics ..................................24 14 maximum t a at various airflows in c (pq4 package only) ..............................25 15 80960hx 208-pin pq4 package thermal characteristics ..................................25 16 fields of 80960hx device id...............................................................................27 17 80960hx device id model types........................................................................27 18 device id version numbers for different steppings ...........................................27 19 operating conditions...........................................................................................29 20 v diff specification for dual power supply requirements (3.3 v, 5 v)...............30 21 80960hx dc characteristics ...............................................................................32 22 80960hx ac characteristics ...............................................................................34 23 ac characteristics notes ....................................................................................36 24 80960hx boundary scan test signal timings....................................................36 25 80960hx boundary scan chain ..........................................................................76 26 data sheet version -006 to -007 revision history..............................................96 80960HA/hd/ht advance information datasheet 1 1.0 about this document this document describes the parametric performance of intels 80960hx embedded superscalar microprocessors. detailed descriptions for functional topics other than parametric performance are published in the i960 ? hx microprocessor users guide (272484). in this document, 80960hx and i960 hx processor refer to the products described in table 1 . throughout this document, information that is specific to each is clearly indicated. 2.0 intels 80960hx processor intels 80960hx processor provides new performance levels while maintaining backward compatibility (pin 1 and software) with the i960 ca/cf processor. this newest member of the family of i960 32-bit, risc-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. this is accomplished by providing processors that can run at the bus speed or faster using intels clock multiplying technology ( table 1 ).the 80960hx core is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler that allows the processor to sustain a throughput of two instructions every core clock, with a peak performance of three instructions per clock. the 80960hx-series comprises three processors, which differ in the ratio of core clock speed to external bus speed. 1. the 80960hx is not drop-in compatible in an 80960cx-based system. customers can design systems that accept either 80960hx or cx processors. figure 1. 80960hx block diagram execution unit programmable bus controller bus request queues six-port register file 32-bit base bus instruction cache 128-bit cache bus instruction prefetch queue interrupt controller control address data memory-side machine bus register-side machine bus memory region configuration multiply/divide unit interrupt port address generation unit data cache 16 kbyte, four-way set-associative 8 kbyte, four-way set-associative guarded memory unit timers jtag port parallel instruction scheduler data ram - 2 kbyte registercache-5to15sets 64-bit src1 bus 64-bit src2 bus 64-bit dst bus 128-bit load bus 128-bit store bus table 1. 80960hx product description product core voltage operating frequency (bus/core) 80960HA 1x 3.3 v * 25/25, 33/33, 40/40 80960hd 2x 3.3 v * 16/32, 25/50, 33/66, 40/80 80960ht 3x 3.3 v * 20/60, 25/75 *processor inputs are 5 v tolerant. 80960HA/hd/ht 2 advance information datasheet in addition to expanded clock frequency options, the 80960hx provides essential enhancements for an emerging class of high-performance embedded applications. features include a larger instruction cache, data cache, and data ram than any other 80960 processor to date. it also boasts a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit, wait state generator, dual programmable timers, once and ieee 1149.1-compliant boundary scan test and debug support, and new instructions. 2.1 the i960 ? processor family the i960 processor family is a 32-bit risc architecture created by intel to serve the needs of embedded applications. the embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and communications. because all members of the i960 processor family share a common core architecture, i960 applications are code-compatible. each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market. 2.2 key 80960hx features 2.2.1 execution architecture independent instruction paths inside the processor allow the execution of multiple, out-of-sequence instructions per clock. register and resource scoreboarding interlocks maintain the logical integrity of sequential instructions that are being executed in parallel. to sustain execution of multiple instructions in each clock cycle, the processor decodes multiple instructions in parallel and simultaneously issues these instructions to parallel processing units. the various processing units are then able to independently access instruction operands in parallel from a common register set. local register cache integrated on-chip provides automatic register management on call/return instructions. upon a call instruction, the processor allocates a set of local registers for the called procedure, then stores the registers for the previous procedure in the on-chip register cache. as additional procedures are called, the cache stores the associated registers such that the most recently called procedure is the first available by the next return ( ret ) instruction. the processor can store up to fifteen register sets, after which the oldest sets are stored (spilled) into external memory. the 80960hx supports the 80960 architecturally-defined branch prediction mechanism. this allows many branches to execute with no pipeline break. with the 80960hxs efficient pipeline, a branch can take as few as zero clocks to execute. the maximum penalty for an incorrect prediction is two core clocks. 2.2.2 pipelined, burst bus a 32-bit high performance bus controller interfaces the 80960hx core to the external memory and peripherals. the bus control unit features a maximum transfer rate of 160 mbytes per second (at a 40 mhz external bus clock frequency). a key advantage of this design is its versatility. the user can independently program the physical and logical attributes of system memory. physical attributes include wait state profile, bus width, and parity. logical attributes include cacheability and big or little endian byte order. internally programmable wait states and 16 separately configurable physical memory regions allow the processor to interface with a variety of memory 80960HA/hd/ht advance information datasheet 3 subsystems with minimum system complexity. to reduce the effect of wait states, the bus design is decoupled from the core. this lets the processor execute instructions while the bus performs memory accesses independently. the bus controllers key features include: ? demultiplexed, burst bus to support most efficient dram access modes ? address pipelining to reduce memory cost while maintaining performance ? 32-, 16- and 8-bit modes to facilitate i/o interfacing ? full internal wait state generation to reduce system cost ? little and big endian support ? unaligned access support implemented in hardware ? three-deep request queue to decouple the bus from the core ? independent physical and logical address space characteristics 2.2.3 on-chip caches and data ram as shown in figure 1 , the 80960hx provides generous on-chip cache and storage features to decouple cpu execution from the external bus. the processor includes a 16 kbyte instruction cache, an 8 kbyte data cache and 2 kbytes of data ram. the caches are organized as 4-way set associative. stores that hit the data cache are written through to memory. the data cache performs write allocation on cache misses. a fifteen-set stack frame cache allows the processor to rapidly allocate and deallocate local registers. all of the on-chip ram sustains a 4-word (128-bit) access every clock cycle. 2.2.4 priority interrupt controller the interrupt unit provides the mechanism for the low latency and high throughput interrupt service essential for embedded applications. a priority interrupt controller provides full programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17 core clocks. the controller supports 31 priority levels. interrupts are prioritized and signaled within 10 core clocks of the request. if the interrupt has a higher priority than the processor priority, the context switch to the interrupt routine would typically complete in another 7 bus clocks. external agents post interrupts via the 8-bit external interrupt port. the interrupt unit also handles the two internal sources from the timers. interrupts can be level- or edge-triggered. 2.2.5 guarded memory unit the guarded memory unit (gmu) provides memory protection without the address translation found in memory management units. the gmu contains two memory protection schemes: one prevents illegal memory accesses, the other detects memory access violations. both signal a fault to the processor. the programmable protection modes are: user read, write or execute; and supervisor read, write or execute. 80960HA/hd/ht 4 advance information datasheet 2.2.6 dual programmable timers the processor provides two independent 32-bit timers, with four programmable clock rates. the user configures the timers via the timer unit registers. these registers are memory-mapped within the 80960hx, addressable on 32-bit boundaries. the timers have a single-shot mode and auto-reload capabilities for continuous operation. each timer has an independent interrupt request to the processors interrupt controller. 2.2.7 processor self test when a system error is detected, the fail pin is asserted, a fail code message is driven onto the address bus, and the processor stops execution at the point of failure. the only way to resume normal operation is to perform a reset operation. because system error generation can occur sometime after the bus confidence test and even after initialization during normal processor operation, the fail pin is high (logic 1) before the detection of a system error. the processor uses only one read bus-transaction to signal the fail code message; the address of the bus transaction is the fail code itself. the fail code is of the form: 0xfeffff nn ; bits 6 to 0 contain a mask recording the possible failures. bit 7, when set to 1, indicates that the mask contains failures from the internal built-in self-test (bist); when 0, the mask indicates other failures. ignore reserved bits 0 and 1. also ignore bits 5 and 6 when bit 7 is clear (=0). the mask is shown in table 2 and table 3 . table 2. fail codes for bist (bit 7 = 1) bit when set: 6 on-chip data-ram failure detected by bist. 5 internal microcode rom failure detected by bist. 4 instruction cache failure detected by bist. 3 data cache failure detected by bist. 2 local-register cache or processor core failure detected by bist. 1 reserved. always zero. 0 reserved. always zero. table 3. remaining fail codes (bit 7 = 0) bit when set: 6 reserved. always one. 5 reserved. always one. 4 a data structure within the imi is not aligned to a word boundary. 3 a system error during normal operation has occurred. 2 the bus confidence test has failed. 1 reserved. always zero. 0 reserved. always zero. 80960HA/hd/ht advance information datasheet 5 2.3 instruction set summary table 4 summarizes the 80960hx instruction set by logical groupings. table 4. 80960hx instruction set data movement arithmetic logical bit / bit field / byte load store move load address conditional select (2) add subtract multiply divide remainder modulo shift extended shift extended multiply extended divide add with carry subtract with carry rotate conditional add (2) conditional subtract (2) and not and and not or exclusive or not or or not nor exclusive nor not nand set bit clear bit not bit alter bit scan for bit span over bit extract modify scan byte for equal byte swap (2) comparison branch call/return fault compare conditional compare compare and increment compare and decrement compare byte (2) compare short (2) test condition code check bit unconditional branch conditional branch compare and branch call call extended call system return branch and link conditional fault synchronize faults debug processor mgmt atomic cache control modify trace controls mark force mark flush local registers modify arithmetic controls modify process controls interrupt enable/ disable (1,2) system control (1) atomic add atomic modify instruction cache control (1,2) data cache control (1,2) notes: 1. 80960hx extensions to the 80960 core instruction set. 2. 80960hx extensions to the 80960cx instruction set. 80960HA/hd/ht 6 advance information datasheet 3.0 package information this section describes the pins, pinouts and thermal characteristics for the 80960hx in the 168-pin ceramic pin grid array (pga) package, 208-pin powerquad2* (pq4). for complete package specifications and information, see the intel packaging handbook (order# 240800). the 80960HA/hd/ht is offered with eigth speeds and two package types ( table 5 ). both the 168-pin ceramic pin grid array (pga) and the 208-pin powerquad2* (pq4) devices are specified for operation at v cc = 3.3 v 0.15 v over a case temperature range of 0 to 85c. table 5. 80960HA/hd/ht package types and speeds package/name device core speed (mhz) bus speed (mhz) order # 168l pga 80960HA 25 a80960HA25 s l2gx 33 a80960HA33 s l2gy 40 a80960HA40 s l2gz 80960hd 32 16 a80960hd32 s l2gg 50 25 a80960hd50 s l2gh 66 33 a80960hd66 s l2gj 80 40 a80960hd80 s l2gk 80960ht 60 20 a80960ht60 75 25 a80960ht75 s l2gp 208l pqfp (alsoknownaspq4) 80960HA 25 fc80960HA25 s l2gu 33 fc80960HA33 s l2gv 40 fc80960HA40 s l2gw 80960hd 32 16 fc80960hd32 s l2gl 50 25 fc80960hd50 s l2gm 66 33 fc80960hd66 s l2gn 80 40 fc80960hd80 s l2lz 80960ht 60 20 fc80960ht60 s l2g2 75 25 fc80960ht75 s l2gt 80960HA/hd/ht advance information datasheet 7 3.1 pin descriptions this section defines the 80960hx pins. table 6 presents the legend for interpreting the pin descriptions in table 7 . all pins float while the processor is in the once mode, except tdo, which can be driven active according to normal jtag specifications. table 6. pin description nomenclature symbol description i input only pin. o output only pin. i/o pin can be input or output. - pin must be connected as indicated for proper device functionality. s(e) synchronous edge sensitive input. this input must meet the setup and hold times relative to clkin to ensure proper operation of the processor. s(l) synchronous level sensitive input. this input must meet the setup and hold times relative to clkin to ensure proper operation of the processor. a(e) asynchronous edge-sensitive input. a(l) asynchronous level-sensitive input. h(...) while the processor bus is in the hold state (holda asserted), the pin: h(1) is driven to v cc h(0) is driven to v ss h(z) floats h(q) continues to be a valid output b(...) while the processor is in the bus backoff state (boff asserted), the pin: b(1) is driven to v cc b(0) is driven to v ss b(z) floats b(q) continues to be a valid output r(...) while the processors reset pin is asserted, the pin: r(1) is driven to v cc r(0) is driven to v ss r(z) floats r(q) continues to be a valid output 80960HA/hd/ht 8 advance information datasheet table 7. 80960hx processor family pin descriptions (sheet 1 of 4) name type description a31:2 o h(z) b(z) r(z) address bus carries the upper 30 bits of the physical address. a31 is the most significant address bit and a2 is the least significant. during a bus access, a31:2 identify all external addresses to word (4-byte) boundaries. the byte enable signals indicate the selected byte in each word. during burst accesses, a3 and a2 increment to indicate successive addresses. d31:0 i/o s(l) h(z) b(z) r(z) data bus carries 32, 16, or 8-bit data quantities depending on bus width configuration. the least significant bit of the data is carried on d0 and the most significant on d31. the lower 8 data lines (d7:0) are used when the bus is configured for 8-bit data. when configured for 16-bit data, d15:0 are used. dp3:0 i/o s(l) h(z) b(z) r(z) data parity carries parity information for the data bus. each parity bit is assigned a group of 8 data bus pins as follows: dp3 generates/checks parity for d31:24 dp2 generates/checks parity for d23:16 dp1 generates/checks parity for d15:8 dp0 generates/checks parity for d7:0 parity information is generated for a processor write cycle and is checked for a processor read cycle. parity checking and polarity are programmable. parity generation/checking is only performed for the size of the data accessed. pchk o h(q) b(q) r(1) parity check indicates the result of a parity check operation. an asserted pchk indicates that the previous bus read access resulted in a parity check error. be3:0 o h(z) b(z) r(1) byte enables select which of the four bytes addressed by a31:2 are active during a bus access. byte enable encoding is dependent on the bus width of the memory region accessed: 32-bit bus: be3 enables d31:24 be2 enables d23:16 be1 enables d15:8 be0 enables d7:0 16-bit bus: be3 becomes byte high enable (enables d15:8) be2 is not used (state is undefined) be1 becomes address bit 1 (a1) be0 becomes byte low enable (enables d7:0) 8-bit bus: be3 is not used (state is undefined) be2 is not used (state is undefined) be1 address bit 1 (a1) be0 address bit 0 (a0) w/r o h(z) b(z) r(0) write/read is low for read accesses and high for write accesses. w/r becomes valid during the address phase of a bus cycle and remains valid until the end of the cycle for non-pipelined accesses. for pipelined accesses, w/r changes state when the next address is presented. 0= read 1= write d/c o h(z) b(z) r(0) data/code indicates that a bus access is a data access or an instruction access. d/c has the same timing as w/r . 0 = code 1=data 80960HA/hd/ht advance information datasheet 9 sup o h(z) b(z) r(1) supervisor access indicates whether the current bus access originates from a request issued while in supervisor mode or user mode. sup canbeusedbythe memory subsystem to isolate supervisor code and data structures from non-supervisor access. 0 = supervisor mode 1 = user mode ads o h(z) b(z) r(1) address strobe indicates a valid address and the start of a new bus access. ads is asserted for the first clock of a bus access. ready i s(l) ready , when enabled for a memory region, is asserted by the memory subsystem to indicate the completion of a data transfer. ready is used to indicate that read data on the bus is valid, or that a write transfer has completed. ready works in conjunction with the internal wait state generator to accommodate various memory speeds. ready is sampled after any programmed wait states: during each data cycle of a burst access during the data cycle of a non-burst access bterm i s(l) burst terminate , when enabled for a memory region, is asserted by the memory subsystem to terminate a burst access in progress. when bterm is asserted, the current burst access is terminated and another address cycle occurs. wait o h(z) b(z) r(1) wait indicates the status of the internal wait-state generator. wait is asserted when the internal wait state generator generates n wad ,n rad ,n wdd and n rdd wait states. wait canbeusedtoderiveawritedatastrobe. blast o h(z) b(z) r(1) burst last indicates the last transfer in a bus access. blast is asserted in the last data transfer of burst and non-burst accesses after the internal wait-state generator reaches zero. blast remains active as long as wait states are inserted via the ready pin. blast becomes inactive after the final data transfer in a bus cycle. dt/r o h(z) b(z) r(0) data transmit/receive indicates direction for data transceivers. dt/r is used with den to provide control for data transceivers connected to the data bus. dt/r is driven low to indicate the processor expects data (a read cycle). dt/r is driven high when the processor is transmitting data (a store cycle). dt/r only changes state when den is high. 0 = data receive 1 = data transmit den o h(z) b(z) r(1) data enable indicates data transfer cycles during a bus access. den is asserted at the start of the first data cycle in a bus access and de-asserted at the end of the last data cycle. den remains asserted for an entire bus request, even when that request spans several bus accesses. for example, a ldq instruction starting at an unaligned quad word boundary is one bus request spanning at least two bus accesses. den remains asserted throughout all the accesses (including ads states) and de-asserts when the iqd instruction request is satisfied. den is used with dt/r to provide control for data transceivers connected to the data bus. den remains asserted for sequential reads from pipelined memory regions. lock o h(z) b(z) r(1) bus lock indicates that an atomic read-modify-write operation is in progress. lock may be used by the memory subsystem to prevent external agents from accessing memory that is currently involved in an atomic operation (e.g., a semaphore). lock is asserted in the first clock of an atomic operation and de-asserted when blast is deasserted in the last bus cycle. table 7. 80960hx processor family pin descriptions (sheet 2 of 4) name type description 80960HA/hd/ht 10 advance information datasheet hold i s(l) hold request signals that an external agent requests access to the processors address, data, and control buses. when hold is asserted, the processor: completes the current bus request. asserts holda and floats the address, data, and control buses. when hold is deasserted, the holda pin is deasserted and the processor reassumes control of the address, data, and control pins. holda o h(1) b(0) r(q) hold acknowledge indicates to an external master that the processor has relinquished control of the bus. the processor grants hold requests and enters the holda state while the reset pin is asserted. holda is never granted while lock is asserted. boff i s(l) bus backoff forces the processor to immediately relinquish control of the bus on the next clock cycle. when ready /bterm is enabled and: when boff is asserted, the address, data, and control buses are floated on the next clock cycle and the current access is aborted. when boff is deasserted, the processor resumes by regenerating the aborted bus access. see figure 16 on page 40 for boff timing requirements. breq o h(q) b(q) r(0) bus request indicates that a bus request is pending in the bus controller. breq does not indicate whether or not the processor is stalled. see bstall for processor stall status. breq can be used with bstall to indicate to an external bus arbiter the processors bus ownership requirements. bstall o h(q) b(q) r(0) bus stall indicates that the processor has stalled pending the result of a request in the bus controller. when bstall is asserted, the processor must regain bus ownership to continue processing (i.e., it can no longer execute strictly out of on-chip cache memory). ct3:0 o h(z) b(z) r(z) cycle type indicates the type of bus cycle currently being started or processor state. ct3:0 encoding follows: cycle type adsct3:0 program-initiated access using 8-bit bus 00000 program-initiated access using 16-bit bus 00001 program-initiated access using 32-bit bus 00010 event-initiated access using 8-bit bus 00100 event-initiated access using 16-bit bus 00101 event-initiated access using 32-bit bus 00110 reserved 00x11 reserved for future products 01xxx reserved 1xxxx xint7:0 i a(e) a(l) external interrupt pins are used to request interrupt service. these pins can be configured in three modes: dedicated mode: each pin is assigned a dedicated interrupt level. dedicated inputs can be programmed to be level (low or high) or edge (rising or falling) sensitive. expanded mode: all eight pins act as a vectored interrupt source. the interrupt pins are level sensitive in this mode. mixed mode: the xint7:5 pins act as dedicated sources and the xint4:0 pins act as the five most significant bits of a vectored source. the least significant bits of the vectored source are set to 010 internally. nmi i a(e) non-maskable interrupt causes a non-maskable interrupt event to occur. nmi is the highest priority interrupt source. nmi is falling edge triggered. table 7. 80960hx processor family pin descriptions (sheet 3 of 4) name type description 80960HA/hd/ht advance information datasheet 11 clkin i clock input provides the time base for the 80960hx. all internal circuitry is synchronized to clkin. all input and output timings are specified relative to clkin. for the 80960hd, the 2x internal clock is derived by multiplying the clkin frequency by 2. for the 80960ht, the 3x internal clock is derived by multiplying the clkin frequency by 3. reset i a(l) reset forces the device into reset. reset causes all external and internal signals to return to their reset state (if defined). the rising edge of reset starts the processor boot sequence. stest i s(l) self test , when asserted during the rising edge of reset , causes the processor to execute its built in self-test. fail o h(q) b(q) r(0) fail indicates a failure of the processors built-in self-test performed during initialization. fail is asserted immediately out of reset and toggles during self-test to indicate the status of individual tests. if self-test passes, fail is de-asserted and the processor branches to the users initialization code. when self-test fails, the fail pin asserts and the processor ceases execution. once i on-circuit emulation control: the processor samples this pin during reset. if it is asserted low at the end of reset, the processor enters once mode. in once mode, the processor stops all clocks and floats all output pins except the tdo pin. once uses an internal pull-up resistor; see r pu definition in table 21 80960hx dc characteristics on page 32 . pull this pin high when not in use. tck i test clock provides the clocking function for ieee 1149.1 boundary scan testing. tdi i test data input is the serial input pin for ieee 1149.1 boundary scan testing. tdi uses an internal pull-up resistor; see r pu definition in table 21 80960hx dc characteristics on page 32 . tdo o test data output is the serial output pin for ieee 1149.1 boundary scan testing. once does not disable this pin. trst i test reset asynchronously resets the test access port (tap) controller. trst must be held low at least 10,000 clock cycles after power-up. one method is to provide trst with a separate power-on-reset circuit. trst includes an internal pull-up resistor; see r pu definition in table 21 80960hx dc characteristics on page 32 . pull this pin low when not in use. tms i test mode select is sampled at the rising edge of tck. tck controls the sequence of tap controller state changes for ieee 1149.1 boundary scan testing. tms uses an internal pull-up resistor; see r pu definition in ta b l e 2 1 80960hx dc characteristics on page 32 . vcc5 i 5 v reference voltage input is the reference voltage for the 5 v-tolerant i/o buffers. connect this signal to +5 v for use with inputs which exceed 3.3 v. when all inputs are from 3.3 v components, connect this signal to 3.3 v. vccpll i pll voltage is the +3.3 vdc analog input for the pll. voldet o voltage detect signal allows external system logic to distinguish between a 5 v 80960cx processor and the 3.3 v 80960hx processor. this signal is active low for a 3.3 v 80960hx (it is high impedance for 5 v 80960cx). this pin is available only on the pga version. 0 = 80960hx 1 = 80960cx table 7. 80960hx processor family pin descriptions (sheet 4 of 4) name type description 80960HA/hd/ht 12 advance information datasheet 3.2 80960hx mechanical data 3.2.1 80960hx pga pinout figure 2 depicts the complete 80960hx pga pinout as viewed from the top side of the component (i.e., pins facing down). figure 3 shows the complete 80960hx pga pinout as viewed from the pin-side of the package (i.e., pins facing up). table 9 lists the 80960hx pin names with package location. see section 4.3, recommended connections on page 30 for specifications and recommended connections. figure 2. 80960hx 168-pin pga pinout view from top (pins facing down) d5 d7 d8 d9 d11 d12 d13 d15 d16 d17 d19 d21 d24 d25 d2 d4 d6 v cc d10 v cc v cc d14 v cc d18 d20 d23 d27 d29 nc d0 v cc v ss v ss v ss v ss v ss v ss v cc d22 d31 ready d26 d28 bterm holda d30 hold be3 v cc ads be2 v ss v cc be1 v ss v cc blast v ss be0 den v ss v cc w/r v ss v cc dt/r a29 lock sup wait bstall a28 a30 breq d/c d3 d1 once v ss vcc5 v cc v ss v ss v ss v ss v ss clkin v cc v ss boff stest dp1 dp3 tck tms v cc pchk v cc vccpll v cc nc nc v cc v ss fail dp0 dp2 voldet trst tdi tdo nc nc cto ct2 ct3 ct1 v ss a2 v cc a22 a25 a20 v ss a3 a5 nmi v cc v ss v ss v ss v ss v ss a24 a31 a26 a4 v cc a6 a8 a9 a10 a11 a12 a14 a15 a17 a18 v cc v cc v cc a13 v cc a16 a19 a21 a23 a27 a7 xint6 xint7 xint4 xint3 xint5 xint0 reset xint2 xint1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a b c d e f g h j k l m n p q r s a b c d e f g h j k l m n p q r s i ? 19xx a80960hx xxxxxxxx ss m 80960HA/hd/ht advance information datasheet 13 figure 3. 80960hx 168-pin pga pinout view from bottom (pins facing up) d5 d7 d8 d9 d11 d12 d13 d15 d16 d17 d19 d21 d24 d25 d2 d4 d6 v cc d10 v cc v cc d14 v cc d18 d20 d23 d27 d29 nc d0 v cc v ss v ss v ss v ss v ss v ss v cc d22 d31 ready d26 d28 bterm holda d30 hold be3 v cc ads be2 v ss v cc be1 v ss v cc blast v ss be0 den v ss v cc w/r v ss v cc dt/r a29 lock sup wait bstall a28 a30 breq d/c d3 d1 once v ss vcc5 v cc v ss v ss v ss v ss v ss clkin v cc v ss boff stest dp1 dp3 tck tms v cc pchk v cc vccpll v cc nc nc v cc v ss fail dp0 dp2 voldet trst tdi tdo nc nc ct0 ct2 ct3 ct1 v ss a2 v cc a22 a25 a20 v ss a3 a5 nmi v cc v ss v ss v ss v ss v ss a24 a31 a26 a4 v cc a6 a8 a9 a10 a11 a12 a14 a15 a17 a18 v cc v cc v cc a13 v cc a16 a19 a21 a23 a27 a7 xint6 xint7 xint4 xint3 xint5 xint0 reset xint2 xint1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a bcdefghjklmnpqrs abcdefghjklmnpqrs package lid 80960HA/hd/ht 14 advance information datasheet table 8. 80960hx 168-pin pga pinout signal name order (sheet 1 of 2) signal name pga pin signal name pga pin signal name pga pin signal name pga pin a2 d16 ads r6 d14 l2 lock s14 a3 d17 be0 r9 d15 l1 nc a9 a4 e16 be1 s7 d16 m1 nc a10 a5 e17 be2 s6 d17 n1 nc b13 a6 f17 be3 s5 d18 n2 nc b14 a7 g16 blast s8 d19 p1 nc d3 a8 g17 boff b1 d20 p2 nmi d15 a9 h17 breq r13 d21 q1 once c3 a10 j17 bstall r12 d22 p3 pchk b8 a11 k17 bterm r4 d23 q2 ready s3 a12 l17 clkin c13 d24 r1 reset a16 a13 l16 ct0 a11 d25 s1 stest b2 a14 m17 ct1 a12 d26 q3 sup q12 a15 n17 ct2 a13 d27 r2 tck b5 a16 n16 ct3 a14 d28 q4 tdi a7 a17 p17 d/c s13 d29 s2 tdo a8 a18 q17 d0 e3 d30 q5 tms b6 a19 p16 d1 c2 d31 r3 trst a6 a20 p15 d2 d2 den s9 v cc b7 a21 q16 d3 c1 dp0 a3 v cc b9 a22 r17 d4 e2 dp1 b3 v cc b11 a23 r16 d5 d1 dp2 a4 v cc b12 a24 q15 d6 f2 dp3 b4 v cc c6 a25 s17 d7 e1 dt/r s11 v cc c14 a26 r15 d8 f1 fail a2 v cc e15 a27 s16 d9 g1 v cc f3 a28 q14 d10 h2 v cc f16 a29 r14 d11 h1 v cc g2 a30 q13 d12 j1 hold r5 v cc h16 a31 s15 d13 k1 holda s4 v cc j2 80960HA/hd/ht advance information datasheet 15 v cc j16 vccpll b10 v ss h3 v ss q10 v cc k2 voldet a5 v ss h15 v ss q11 v cc k16 v ss a1 v ss j3 w/r s10 v cc m2 v ss c4 v ss j15 wait s12 v cc m16 v ss c7 v ss k3 xint0 b15 v cc n3 v ss c8 v ss k15 xint1 a15 v cc n15 v ss c9 v ss l3 xint2 a17 v cc q6 v ss c10 v ss l15 xint3 b16 v cc r7 v ss c11 v ss m3 xint4 c15 v cc r8 v ss c12 v ss m15 xint5 b17 v cc r10 v ss f15 v ss q7 xint6 c16 v cc r11 v ss g3 v ss q8 xint7 c17 vcc5 c5 v ss g15 v ss q9 table 8. 80960hx 168-pin pga pinout signal name order (sheet 2 of 2) signal name pga pin signal name pga pin signal name pga pin signal name pga pin 80960HA/hd/ht 16 advance information datasheet table 9. 80960hx 168-pin pga pinout pin number order (sheet 1 of 2) pga pin signal name pga pin signal name pga pin signal name pga pin signal name a1 v ss b14 nc e15 v cc k15 v ss a2 fail b15 xint0 e16 a4 k16 v cc a3 dp0 b16 xint3 e17 a5 k17 a11 a4 dp2 b17 xint5 f1 d8 l1 d15 a5 voldet c1 d3 f2 d6 l2 d14 a6 trst c2 d1 f3 v cc l3 v ss a7 tdi c3 once f15 v ss l15 v ss a8 tdo c4 v ss f16 v cc l16 a13 a9 nc c5 vcc5 f17 a6 l17 a12 a10 nc c6 v cc g1 d9 m1 d16 a11 ct0 c7 v ss g2 v cc m2 v cc a12 ct1 c8 v ss g3 v ss m3 v ss a13 ct2 c9 v ss g15 v ss m15 v ss a14 ct3 c10 v ss g16 a7 m16 v cc a15 xint1 c11 v ss g17 a8 m17 a14 a16 reset c12 v ss h1 d11 n1 d17 a17 xint2 c13 clkin h2 d10 n2 d18 b1 boff c14 v cc h3 v ss n3 v cc b2 stest c15 xint4 h15 v ss n15 v cc b3 dp1 c16 xint6 h16 v cc n16 a16 b4 dp3 c17 xint7 h17 a9 n17 a15 b5 tck d1 d5 j1 d12 p1 d19 b6 tms d2 d2 j2 v cc p2 d20 b7 v cc d3 nc j3 v ss p3 d22 b8 pchk d15 nmi j15 v ss p15 a20 b9 v cc d16 a2 j16 v cc p16 a19 b10 vccpll d17 a3 j17 a10 p17 a17 b11 v cc e1 d7 k1 d13 q1 d21 b12 v cc e2 d4 k2 v cc q2 d23 b13 nc e3 d0 k3 v ss q3 d26 80960HA/hd/ht advance information datasheet 17 q4 d28 q16 a21 r11 v cc s6 be2 q5 d30 q17 a18 r12 bstall s7 be1 q6 v cc r1 d24 r13 breq s8 blast q7 v ss r2 d27 r14 a29 s9 den q8 v ss r3 d31 r15 a26 s10 w/r q9 v ss r4 bterm r16 a23 s11 dt/r q10 v ss r5 hold r17 a22 s12 wait q11 v ss r6 ads s1 d25 s13 d/c q12 sup r7 v cc s2 d29 s14 lock q13 a30 r8 v cc s3 ready s15 a31 q14 a28 r9 be0 s4 holda s16 a27 q15 a24 r10 v cc s5 be3 s17 a25 table 9. 80960hx 168-pin pga pinout pin number order (sheet 2 of 2) pga pin signal name pga pin signal name pga pin signal name pga pin signal name 80960HA/hd/ht 18 advance information datasheet 3.2.2 80960hx pq4 pinout figure 4. 80960hx 208-pin pq4 pinout pin 1 pin 208 pin 52 pin 53 pin 104 pin 157 pin 156 v cc v ss v ss v cc fai l once v ss v cc boff v cc d0 d1 d2 d3 v ss v cc v ss v cc d4 d5 d6 d7 v ss v cc d8 d9 d10 v cc v ss v cc d12 d13 d14 d15 v cc d16 d17 d18 d19 v ss v cc d21 d22 d23 pin 105 v ss d24 d25 d26 d27 v ss v cc v cc d28 d29 d30 d31 v ss v cc bterm ready hold holda v ss v cc v ss v cc v ss v cc ads be3 be2 v ss v cc be1 be0 blast den v ss v cc w/r dt/r wait bstall v cc v ss v ss v cc d/c sup v ss lock breq v cc v cc v ss v ss v ss v cc v cc v ss a2 a3 v cc v ss a4 a5 a6 a7 v cc v ss a8 a9 a10 a11 v cc v ss a12 a13 a14 a15 v cc v ss v ss v cc a16 a17 a18 a19 v cc v ss a20 a21 a22 a23 v cc v ss v cc v ss a24 a25 a26 a27 v cc v ss a28 a29 a30 v ss v cc nmi xint7 xint6 xint5 xint4 v ss v cc xint3 xint2 xint1 xint0 v ss v cc v ss v cc reset clkin vccpll v ss v cc ct3 ct2 ct1 ct0 v ss v cc v ss v cc tdo pchk v ss tdi tms trst tck v ss v cc vcc5 v cc v ss v cc dp3 dp2 v cc v ss dp0 dp1 stest d11 v ss a31 v ss v cc d20 v cc v ss v ss i xxxxxxxx ss m ?19xx i960 ? fc80960hx v cc v ss 80960HA/hd/ht advance information datasheet 19 table 10. 80960hx pq4 pinout signal name order (sheet 1 of 2) signal name pq4 pin signal name pq4 pin signal name pq4 pin signal name pq4 pin a2 151 be0 83 d16 39 pchk 189 a3 150 be1 82 d17 40 ready 68 a4 147 be2 79 d18 41 reset 174 a5 146 be3 78 d19 42 stest 208 a6 145 blast 84 d20 45 sup 97 a7 144 boff 10 d21 50 tck 194 a8 141 breq 100 d22 51 tdi 191 a9 140 bstall 91 d23 52 tdo 188 a10 139 bterm 67 d24 54 tms 192 a11 138 clkin 175 d25 55 trst 193 a12 135 ct0 183 d26 56 v cc 1 a13 134 ct1 182 d27 57 v cc 4 a14 133 ct2 181 d28 61 v cc 9 a15 132 ct3 180 d29 62 v cc 11 a16 127 d/c 96 d30 63 v cc 17 a17 126 d0 12 d31 64 v cc 19 a18 125 d1 13 den 85 v cc 25 a19 124 d2 14 dp0 206 v cc 31 a20 121 d3 15 dp1 207 v cc 33 a21 120 d4 20 dp2 203 v cc 38 a22 119 d5 21 dp3 202 v cc 44 a23 118 d6 22 dt/r 89 v cc 46 a24 113 d7 23 fail 5 v cc 49 a25 112 d8 26 v cc 59 a26 111 d9 27 v cc 60 a27 110 d10 28 v cc 66 a28 107 d11 29 hold 69 v cc 71 a29 106 d12 34 holda 72 v cc 74 a30 105 d13 35 lock 99 v cc 76 a31 104 d14 36 nmi 159 v cc 81 ads 77 d15 37 once 6 v cc 87 80960HA/hd/ht 20 advance information datasheet v cc 92 v cc 187 v ss 70 v ss 164 v cc 95 v cc 196 v ss 73 v ss 170 v cc 101 v cc 199 v ss 75 v ss 172 v cc 102 v cc 201 v ss 80 v ss 178 v cc 109 v cc 204 v ss 86 v ss 184 v cc 115 vcc5 197 v ss 93 v ss 186 v cc 117 vccpll 177 v ss 94 v ss 190 v cc 123 v ss 2 v ss 98 v ss 195 v cc 128 v ss 3 v ss 103 v ss 198 v cc 131 v ss 7v ss 108 v ss 200 v cc 137 v ss 8 v ss 114 v ss 205 v cc 143 v ss 16 v ss 116 w/r 88 v cc 149 v ss 18 v ss 122 wait 90 v cc 153 v ss 24 v ss 129 xint0 169 v cc 154 v ss 30 v ss 130 xint1 168 v cc 158 v ss 32 v ss 136 xint2 167 v cc 165 v ss 43 v ss 142 xint3 166 v cc 171 v ss 47 v ss 148 xint4 163 v cc 173 v ss 48 v ss 152 xint5 162 v cc 176 v ss 53 v ss 155 xint6 161 v cc 179 v ss 58 v ss 156 xint7 160 v cc 185 v ss 65 v ss 157 table 10. 80960hx pq4 pinout signal name order (sheet 2 of 2) signal name pq4 pin signal name pq4 pin signal name pq4 pin signal name pq4 pin 80960HA/hd/ht advance information datasheet 21 table 11. 80960hx pq4 pinout pin number order (sheet 1 of 2) pq4 pin signal name pq4 pin signal name pq4 pin signal name pq4 pin signal name 1 v cc 31 v cc 61 d28 91 bstall 2 v ss 32 v ss 62 d29 92 v cc 3 v ss 33 v cc 63 d30 93 v ss 4 v cc 34 d12 64 d31 94 v ss 5 fail 35 d13 65 v ss 95 v cc 6 once 36 d14 66 v cc 96 d/c 7 v ss 37 d15 67 bterm 97 sup 8 v ss 38 v cc 68 ready 98 v ss 9 v cc 39 d16 69 hold 99 lock 10 boff 40 d17 70 v ss 100 breq 11 v cc 41 d18 71 v cc 101 v cc 12 d0 42 d19 72 holda 102 v cc 13 d1 43 v ss 73 v ss 103 v ss 14 d2 44 v cc 74 v cc 104 a31 15 d3 45 d20 75 v ss 105 a30 16 v ss 46 v cc 76 v cc 106 a29 17 v cc 47 v ss 77 ads 107 a28 18 v ss 48 v ss 78 be3 108 v ss 19 v cc 49 v cc 79 be2 109 v cc 20 d4 50 d21 80 v ss 110 a27 21 d5 51 d22 81 v cc 111 a26 22 d6 52 d23 82 be1 112 a25 23 d7 53 v ss 83 be0 113 a24 24 v ss 54 d24 84 blast 114 v ss 25 v cc 55 d25 85 den 115 v cc 26 d8 56 d26 86 v ss 116 v ss 27 d9 57 d27 87 v cc 117 v cc 28 d10 58 v ss 88 w/r 118 a23 29 d11 59 v cc 89 dt/r 119 a22 30 v ss 60 v cc 90 wait 120 a21 80960HA/hd/ht 22 advance information datasheet 121 a20 143 v cc 165 v cc 187 v cc 122 v ss 144 a7 166 xint3 188 tdo 123 v cc 145 a6 167 xint2 189 pchk 124 a19 146 a5 168 xint1 190 v ss 125 a18 147 a4 169 xint0 191 tdi 126 a17 148 v ss 170 v ss 192 tms 127 a16 149 v cc 171 v cc 193 trst 128 v cc 150 a3 172 v ss 194 tck 129 v ss 151 a2 173 v cc 195 v ss 130 v ss 152 v ss 174 reset 196 v cc 131 v cc 153 v cc 175 clkin 197 vcc5 132 a15 154 v cc 176 v cc 198 v ss 133 a14 155 v ss 177 vccpll 199 v cc 134 a13 156 v ss 178 v ss 200 v ss 135 a12 157 v ss 179 v cc 201 v cc 136 v ss 158 v cc 180 ct3 202 dp3 137 v cc 159 nmi 181 ct2 203 dp2 138 a11 160 xint7 182 ct1 204 v cc 139 a10 161 xint6 183 ct0 205 v ss 140 a9 162 xint5 184 v ss 206 dp0 141 a8 163 xint4 185 v cc 207 dp1 142 v ss 164 v ss 186 v ss 208 stest table 11. 80960hx pq4 pinout pin number order (sheet 2 of 2) pq4 pin signal name pq4 pin signal name pq4 pin signal name pq4 pin signal name 80960HA/hd/ht advance information datasheet 23 3.3 package thermal specifications the 80960hx is specified for operation when t c (case temperature) is within the range of 0cC85c. t c may be measured in any environment to determine whether the 80960hx is within the specified operating range. measure the case temperature at the center of the top surface, opposite the pins. refer to figure 5 . t a (ambient temperature) is calculated from q ca (thermal resistance from case to ambient) using the equation: t a =t c Cp* q ca table 12 shows the maximum t a allowable (without exceeding t c ) at various airflows and operating frequencies (f clkin ). note that t a is greatly improved by attaching fins or a heatsink to the package. p (maximum power consumption) is calculated by using the typical i cc as tabulated in section 4.6, dc specifications on page 32 and v cc of 3.3 v. figure 5. measuring 80960hx pga case temperature measure pga/pq4 temperature at center of top surface 80960HA/hd/ht 24 advance information datasheet table 12. maximum t a at various airflows in c (pga package only) airflow-ft/min (m/sec) f clkin (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) core 1x bus clock t a with heatsink* 25 33 40 69 63 59 74 70 67 78 75 73 79 77 75 80 79 77 80 79 77 t a without heatsink 25 33 40 64 56 50 67 62 56 71 67 63 74 70 67 75 72 69 76 74 71 core 2x bus clock t a with heatsink* 16 25 33 40 68 58 49 41 73 66 60 55 77 73 69 65 79 75 71 68 80 77 74 72 80 77 74 72 t a without heatsink 16 25 33 40 62 49 38 27 66 56 46 38 71 62 55 48 73 66 60 55 75 68 63 58 76 71 66 62 core 3x bus clock t a with heatsink* 20 25 53 45 63 58 71 67 73 70 76 73 76 73 t a without heatsink 20 25 43 33 51 42 58 51 63 58 66 61 68 64 *0.285 high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). table 13. 80960hx 168-pin pga package thermal characteristics thermal resistance c/watt parameter airflow ft./min (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.07) 800 (4.06) 1000 (5.07) q junction-to-case (case measured as shown in figure 5 ) 1.51.51.51.51.51.5 q case-to-ambient (no heatsink) 17 14 11 9 8 7 q case-to-ambient (with heatsink)* 1396544 notes: 1. this table applies to 80960hx pga plugged into socket or soldered directly to board. 2. q ja = q jc + q ca *0.285 high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). q jc q ja 80960HA/hd/ht advance information datasheet 25 table 14. maximum t a at various airflows in c (pq4 package only) airflow-ft/min (m/sec) f clkin (mhz) 0 (0) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) 1000 (5.07) core 1x bus clock t a with heatsink* 25 33 40 71 67 63 76 74 71 79 77 75 79 77 75 80 79 77 80 79 77 t a without heatsink 25 33 40 70 65 61 73 68 65 75 72 69 75 72 69 76 74 71 76 74 71 core 2x bus clock t a with heatsink* 16 25 33 40 71 62 55 48 76 71 66 62 79 75 71 68 79 75 71 68 80 77 74 72 80 77 74 72 t a without heatsink 16 25 33 40 69 60 52 42 72 64 57 51 75 68 63 58 75 68 63 58 76 71 66 62 76 71 66 62 core 3x bus clock t a with heatsink* 20 25 58 51 68 64 73 70 73 70 76 73 76 73 t a without heatsink 20 25 56 48 61 55 66 61 66 61 68 64 68 64 *0.285 high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). table 15. 80960hx 208-pin pq4 package thermal characteristics thermal resistance c/watt parameter airflow ft./min (m/sec) 0 (0) 200 (1.01) 400 (2.03) 600 (3.07) 800 (4.06) 1000 (5.07) q junction-to-case (case measured as shown in figure 5 ) 111111 q case-to-ambient (no heatsink) 12 10 8 8 7 7 q case-to-ambient (with heatsink)* 1175544 notes: 1. this table applies to 80960hx pq4 plugged into socket or soldered directly to board. 2. q ja = q jc + q ca *0.285 high unidirectional heatsink (ai alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). q jc q ja 80960HA/hd/ht 26 advance information datasheet 3.4 heat sink adhesives intel recommends silicone-based adhesives to attach heat sinks to the pga package. there is no particular recommendation concerning the pq4 package. 3.5 powerquad4 plastic package the 80960hx family is available in an improved version of the common 208-lead sqfp plastic package called the powerquad4* (pq4). the pq4 package dimensions and lead pitch are identical to the sqfp package and the former pq2 package, so the pq4 fits into the same board footprint. the advantage of the pq4 package is the superior thermal conductivity that allows the plastic version of the 80960hx to operate with the same 0-85c temperature specifications as the more expensive ceramic pga package. the pq4 package integrates a copper heat sink within the package to dissipate heat effectively. see table 14 and table 15 . 3.6 stepping register information the memory-mapped register at ff008710h contains the 80960hx device id. the id is identical to the id obtained from a jtag query. figure 6 defines the current 80960hx device ids. the value for device identification is compliant with the ieee 1149.1 specification and intel standards. table 16 describes the fields of the device id. figure 6. 80960hx device identification register 28 24 20 40 16 12 8 1 1 0 0 1 0 0 0 0 0 0 0 manufacturer id part number version model gen product ty p e v cc 0 1 0 0 0 0 1 0 0 0 1 1 80960HA/hd/ht advance information datasheet 27 table 16. fields of 80960hx device id field value definition version see ta b l e 1 8 indicates major stepping changes. v cc 1 = 3.3 v device indicates that a device is 3.3 v. product type 00 0100 (indicates i960 cpu) designates type of product. generation type 0010 = h-series indicates the generation (or series) the product belongs to. model see ta b l e 1 7 indicates member within a series and specific model information. manufacturer id 000 0000 1001 (indicates intel) manufacturer id assigned by ieee. table 17. 80960hx device id model types device version v cc product gen. model manufacturer id 1 80960HA see ta b l e 1 8 1 000100 0010 00000 00000001001 1 80960hd 1 000100 0010 00001 00000001001 1 80960ht 1 000100 0010 00010 00000001001 1 table 18. device id version numbers for different steppings stepping version a0 0000 a1 0001 a2 0001 b0, b2 0010 this data sheet applies to the b2 stepping. 80960HA/hd/ht 28 advance information datasheet 3.7 sources for accessories the following is a list of suggested sources for 80960hx accessories. this is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. sockets ? 3m textool test and interconnection products 6801 river place blvd. ms 130-3n-29 austin, tx 78726-9000 (800) 328-0411 fax: (800) 932-9373 ? concept mfg, inc. (decoupling sockets) 400 walnut st. suite 609 redwood city, ca 94063 (415) 365-1162 fax: (415) 365-1164 heatsinks/fins ? thermalloy, inc. 2021 west valley view lane dallas, tx 75234-8993 (972) 243-4321 fax: (972) 241-4656 ? wakefield engineering, inc. 60 audubon road wakefield, ma 01880 (617) 245-5900 fax: (617) 246-0874 ? aavid thermal technologies, inc. one kool path laconia, nh 03247-0400 (603) 523-3400 80960HA/hd/ht advance information datasheet 29 4.0 electrical specifications 4.1 absolute maximum ratings 4.2 operating conditions parameter maximum rating storage temperature C65 oc to +150 oc case temperature under bias C65oc to +110oc supply voltage with respect to v ss C0.5 v to + 4.6 v voltage on vcc5 with respect to v ss C0.5 v to + 6.5 v voltage on other pins with respect to v ss C0.5 v to vcc5 + 0.5 v notice: this document contains information on products in the sampling and initial production phases of development. it is valid for the devices indicated in the revision history. the specifications within this data sheet are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 19. operating conditions symbol parameter min max units v cc supply voltage 3.15 3.45 v vcc5 input protection bias 3.15 5.5 v f clkin 1xcore input clock frequency - 1x core (80960HA) 16 40 mhz f clkin 2xcore input clock frequency - 2x core (80960hd) 16 40 mhz f clkin 3xcore input clock frequency - 3x core (80960ht) 16 25 mhz t c case temp under bias (pga and pq4 packages) 0 85 o c 80960HA/hd/ht 30 advance information datasheet 4.3 recommended connections power and ground connections must be made to multiple v cc and v ss (gnd) pins. every 80960hx-based circuit board should include power (v cc ) and ground (v ss ) planes for power distribution. every v cc pin must be connected to the power plane; every v ss pin must be connected to the ground plane. pins identified as nc no connect pins must not be connected in the system. liberal decoupling capacitance should be placed near the 80960hx. the processor can cause transient power surges when its output buffers transition, particularly when connected to large capacitive loads. low inductance capacitors and interconnects are recommended for best high-frequency electrical performance. inductance can be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible. capacitors specifically designed for pga packages offer the lowest possible inductance. for reliable operation, always connect unused inputs to an appropriate signal level. in particular, any unused interrupt (xint7:0 ,nmi ) input should be connected to v cc through a pull-up resistor, as should bterm if not used. pull-up resistors should be in the range of 20 k w for each pin tied high. if ready or hold are not used, the unused input should be connected to ground. n.c. pins must always remain unconnected. 4.4 vcc5 pin requirements (v diff ) in mixed-voltage systems that drive 80960hx processor inputs in excess of 3.3 v, the vcc5 pin must be connected to the systems 5 v supply. to limit current flow into the vcc5 pin, there is a limit to the voltage differential between the vcc5 pin and the other v cc pins. the voltage differential between the 80960hx vcc5 pin and its 3.3 v v cc pins should never exceed 2.25 v. this limit applies to power-up, power-down, and steady-state operation. table 20 outlines this requirement. meeting this requirement ensures proper operation and guarantees that the current draw into the vcc5 pin does not exceed the i cc5 specification. if the voltage difference requirements cannot be met due to system design limitations, an alternate solution may be employed. as shown in figure 7 , a minimum of 100 w series resistor may be used to limit the current into the vcc5 pin. this resistor ensures that current drawn by the vcc5 pin does not exceed the maximum rating for this pin. this resistor is not necessary in systems that can guarantee the v diff specification. in 3.3 v-only systems and systems that drive 80960hx pins from 3.3 v logic, connect the vcc5 pin directly to the 3.3 v v cc plane. figure 7. vcc5 current-limiting resistor +5 v (0.25 v) vcc5 pin 100 w (5%, 0.5 w) table 20. v diff specification for dual power supply requirements (3.3 v, 5 v) sym parameter min max units notes v diff vcc5-v cc difference 2.25 v vcc5 input should not exceed v cc by more than 2.25 v during power-up and power-down, or during steady-state operation. 80960HA/hd/ht advance information datasheet 31 4.5 vccpll pin requirements if the voltage on the vccpll power supply pin exceeds the v cc pin voltage by 0.5 v at any time, including the power up and power down sequences, excessive currents can permanently damage on-chip electrostatic discharge (esd) protection diodes. the damage can accumulate over multiple episodes. pragmatically, this problem only occurs when the vccpll and v cc pins are driven by separate power supplies or voltage regulators. applications that use one power supply for vccpll and v cc are not typically at risk. verify that your application does not allow the vccpll voltage to exceed v cc by 0.5 v. the vccpl low-pass filter recommended in the developers manual does not promote this problem. 80960HA/hd/ht 32 advance information datasheet 4.6 dc specifications table 21. 80960hx dc characteristics (sheet 1 of 2) per the conditions described in section 4.3, recommended connections on page 30 . symbol parameter min typ max units notes v il input low voltage C 0.3 +0.8 v v ih input high voltage 2.0 vcc5 + 0.3 v v ol output low voltage all outputs except fail 0.4 0.2 v i ol =3ma i ol = 100 m a v ol output low voltage fail pin 0.4 v i ol =5ma v oh output high voltage 2.4 v cc C0.2 v v i oh =C3ma i oh = C100 m a i li input leakage current non-test inputs tdi, tms, trst and once -1 1 -110 a a 0 v in v cc v in =0v i lo output leakage current non-test outputs tdo pin 1 5 a a 0.45 v out v cc 0.45 v out v cc i cc active (power supply) 80960HA 25 33 40 80960hd 32 50 66 80 80960ht 60 75 579 765 927 631 985 1300 1578 1165 1455 ma (4,5) i cc active (thermal) 80960HA 25 33 40 80960hd 32 50 66 80 80960ht 60 75 392 518 628 413 645 851 1034 752 938 ma (4,6) i cc te s t (reset mode) 80960HA 25 33 40 80960hd 32 50 66 80 80960ht 60 75 330 436 528 382 595 785 955 702 878 ma (7,8) i cc te s t (once mode) 25 ma (7) 80960HA/hd/ht advance information datasheet 33 i cc5 current on the vcc5 pin 80960HA 80960hd 80960ht 200 200 200 a (9) c in input capacitance for: pq4 pga 12 12 pf pf f c = 1 mhz (10) c out output capacitance of each output pin 12 pf f c = 1 mhz (3,10) c i/o i/o pin capacitance 12 pf f c = 1 mhz (10) r pu internal pull-up resistance for once ,tms,tdiand trst 30 65 100 k w notes: 1. i cc maximum is measured at worst case frequency, v cc , and temperature, with device operating and outputs loaded to the test conditions described in section 4.7.1, ac test conditions on page 37 . 2. i cc typical is not tested. 3. output capacitance is the capacitive load of a floating output. 4. measured with device operating and outputs loaded to the test conditions in figure 8 ac test load on page 37 . input signals rise to v cc and fall to v ss . 5. i cc active (power supply) value is provided for selecting your systems power supply. it is measured using one of the worst case instruction mixes with v cc = 3.45 v. this parameter is characterized but not tested. 6. i cc active (thermal) value is provided for your systems thermal management. typical i cc is measured with v cc = 3.3 v and temperature = 25c. this parameter is characterized but not tested. 7. i cc test (power modes) refers to the i cc values that are tested when the 80960HA/hd/ht is in reset mode or once mode with v cc =3.45v. 8. worst case is v cc =3.45v,0c. 9. i cc5 is tested at v cc =3.0v,vcc5=5.25v. 10.pin capacitance is characterized, but not tested. table 21. 80960hx dc characteristics (sheet 2 of 2) per the conditions described in section 4.3, recommended connections on page 30 . symbol parameter min typ max units notes 80960HA/hd/ht 34 advance information datasheet 4.7 ac specifications table 22. 80960hx ac characteristics (sheet 1 of 2) per conditions in section 4.2, operating conditions on page 29 and section 4.7.1, ac test conditions on page 37 . symbol parameter min max units notes input clock (1,7) t f clkin frequency 80960HA 80960hd 80960ht 16 16 16 40 40 25 mhz mhz mhz t clkin period 80960HA 80960hd 80960ht 25 25 40 62.5 62.5 62.5 ns ns ns t cs clkin period stability -250 +250 ps (11) t ch clkin high time 8 ns (11) t cl clkin low time 80960HA 80960hd 80960ht 8 8 8 ns ns ns (11) t cr clkin rise time 0 4 ns (11) t cf clkin fall time 0 4 ns (11) synchronous outputs (1,2,3,6) t ov1 ,t oh1 output valid delay and output hold for all outputs except dt/r ,blast and breq for 3.3 v and 5 v inputs and i/os. 1.5 9.5 ns t ov2 ,t oh2 output valid delay and output hold for dt/r 80960HA 80960hd 80960ht t/2 + 1.5 3t/4 + 1.5 5t/6 + 1.5 t/2 + 9.5 3t/4 + 9.5 5t/6 + 9.5 ns ns ns t ov3 ,t oh3 output valid delay and output hold for blast 1.5 9 ns t ov4 ,t oh4 output valid delay and output hold for breq 0.5 9 ns t ov5 ,t oh5 output valid delay and output hold for a3:2 1.5 8.5 t of output float for all outputs 1.5 9 ns (11) synchronous inputs (1,7,8,9) t is1 input setup for all inputs except ready ,bterm , hold, and boff 2.5 ns t ih1 input hold for all inputs except ready ,bterm , hold, and boff 2.5 ns t is2 input setup for ready ,bterm , hold, and boff 6ns note: see table 23 ac characteristics notes on page 36 for all notes related to ac specifications. 80960HA/hd/ht advance information datasheet 35 t ih2 input hold for ready ,bterm , hold, and boff 2.5 ns relative output timings (1,2,3,6,10) t avsh1 a31:2 valid to ads rising t C 5 t + 5 ns (10) t avsh2 be3:0 ,w/r ,sup ,d/c valid to ads rising t C 5 t + 5 ns (10) t avel1 a31:2 valid to den falling t C 5 t + 5 ns (10) t avel2 be3:0 ,w/r ,sup validtoden falling t C 5 t + 5 ns (10) t nlqv wait falling to output data valid -5 5 ns (10) t dvnh output data valid to wait rising -5 + n*t 5 + n*t ns (4,10) t nlnh wait falling to wait rising -4 + n*t 4 + n*t ns (4,10) t nhqx output data hold after wait rising -5 + (n+1)*t 5 + (n+1)*t ns (5,10) t ehtv dt/r hold after den high t/2 C 5 infinite ns (10) t tvel dt/r valid to den falling 80960HA 80960hd 80960ht t/2 C 4 t/4 C 4 t/6 C 4 ns ns ns (10) relative input timings (1,7,10) t is7 xint7:0 ,nmi input setup 6 ns (9) t ih7 xint7:0 ,nmi input hold 2.5 ns (9) t is8 reset input setup 3 ns (8) t ih8 reset input hold t/4 + 1 ns (8) table 22. 80960hx ac characteristics (sheet 2 of 2) per conditions in section 4.2, operating conditions on page 29 and section 4.7.1, ac test conditions on page 37 . symbol parameter min max units notes note: see table 23 ac characteristics notes on page 36 for all notes related to ac specifications. 80960HA/hd/ht 36 advance information datasheet table 23. ac characteristics notes notes: 1. see section 4.8, ac timing waveforms on page 38 for waveforms and definitions. 2. see figure 25 output delay or hold vs. load capacitance on page 44 for capacitive derating information for output delays and hold times. 3. see figure 22 rise and fall time derating at 85c and minimum v cc on page 43 for capacitive derating information for rise and fall times. 4. where n is the number of n rad ,n rdd ,n wad or n wdd wait states that are programmed in the bus controller region table. wait never goes active when there are no wait states in an access. 5. n = number of wait states inserted with ready . 6. these specifications are guaranteed by the processor. 7. these specifications must be met by the system for proper operation of the processor. 8. reset is an asynchronous input that has no required setup and hold time for proper operation. however, to guarantee the device exits the reset mode synchronized to a particular clock edge, the rising edge of reset must meet setup and hold times to the rising edge of the clkin. 9. the interrupt pins are synchronized internally by the 80960hx. they have no required setup or hold times for proper operation. these pins are sampled by the interrupt controller every clock and must be active for at least two consecutive clkin rising edges when asserting them asynchronously. to guarantee recognition at a particular clock edge, the setup and hold times shown must be met. 10.relative output timings are not tested. 11.not tested. 12.the processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for the following signals: a31:4, sup ,ct3:0,d/c ,lock ,w/r , be3:0 . table 24. 80960hx boundary scan test signal timings symbol parameter min max units notes t bsf tck frequency 0 8 mhz t bsc tck period 125 infinite ns t bsch tck high time 40 ns measured at 1.5 v (1) t bscl tck low time 40 ns measured at 1.5 v (1) t bscr tck rise time 8 ns 0.8 v to 2.0 v (1) t bscf tck fall time 8 ns 2.0 v to 0.8 v (1) t bsis1 input setup to tck tdi, tms 8ns t bsih1 input hold from tck tdi, tms 10 ns t bsov1 tdo valid delay 3 30 ns t bsof1 tdo float delay 36 ns (1) t bsov2 all outputs (non-test) valid delay 330ns relative to tck t bsof2 all outputs (non-test) float delay 36 ns relative to tck (1) t bsis2 input setup to tck - all inputs (non-test) 8ns t bsih2 input hold from tck - all inputs (non-test) 10 ns note: 1. not tested. 80960HA/hd/ht advance information datasheet 37 4.7.1 ac test conditions ac values are derived using the 50 pf load shown in figure 8 . figure25outputdelayorholdvs. load capacitance on page 44 , shows how timings vary with load capacitance. input waveforms (except for clkin) are assumed to have a rise and fall time of 2nsfrom0.8vto2.0v. figure 8. ac test load output pin c l = 50 pf for all signals c l 80960HA/hd/ht 38 advance information datasheet 4.8 ac timing waveforms figure 9. clkin waveform figure 10. output delay waveform figure 11. output delay waveform 2.0 v 1.5 v 0.8 v t cf t ch t cl t t cr clkin outputs: 1.5 v 1.5 v t ov1 min max t oh1 1.5 v 1.5 v a31:2, d31:0 write only, dp3:0 write only pchk ,be3:0 ,w/r ,d/c , sup ,ads ,den , lock ,holda,breq,bstall, ct3:0, fail ,wait , blast clkin 1.5 v 1.5 v dt/r min max t oh2 1.5 v 1.5 v t ov2 80960HA/hd/ht advance information datasheet 39 figure 12. output float waveform figure 13. input setup and hold waveform figure 14. nmi ,xint7:0 input setup and hold waveform min max t of outputs: a31:2, d31:0 write only, dp3:0 write only pchk , be3:0 ,w/r ,d/c , sup ,ads ,den , lock ,holda, ct3:0, wait ,blast ,dt/r clkin 1.5 v 1.5 v clkin inputs: 1.5 v 1.5 v 1.5 v valid t is t ih ready , hold, bterm , boff , d31:0 on reads, min min dp3:0onreads,reset clkin 1.5 v 1.5 v 1.5 v valid t is t ih nmi , xint7:0 min min 1.5 v 1.5 v a b a note: a and b edges are established by de-assertion of reset .see figure 29 cold reset waveform on page 46 . 80960HA/hd/ht 40 advance information datasheet figure 15. hold acknowledge timings figure 16. bus backoff (boff ) timings clkin 1.5 v 1.5 v 1.5 v hold t is t ih 1.5 v t ih t is holda t ov1 min min min min t ov1 max min max min t oh1 t oh1 t ov t oh output delay - the maximum output delay is referred to as the output valid delay (t ov ). the minimum output delay is referred to as the output hold (t oh ). t is t ih input setup and hold - the input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v clkin 1.5 v 1.5 v 1.5 v boff t is t ih t ih t is 1.5 v 1.5 v 1.5 v 80960HA/hd/ht advance information datasheet 41 figure 17. tck waveform figure 18. input setup and hold waveforms for t bsis1 and t bsih1 2.0 v 1.5 v 0.8 v t bscf t bsch t bscl t bsc t bscr tclk inputs: tms 1.5 v 1.5 v 1.5 v tdi 1.5 v 1.5 v valid t bsis1 t bsih1 80960HA/hd/ht 42 advance information datasheet figure 19. output delay and output float for t bsov1 and t bsof1 figure 20. output delay and output float waveform for t bsov2 and t bsof2 figure 21. input setup and hold waveform for t bsis2 and t bsih2 tck 1.5 v 1.5 v 1.5 v 1.5 v t bsov1 tdo valid t bsof1 tck 1.5 v 1.5 v 1.5 v 1.5 v t bsov2 non-test valid t bsof2 outputs tck non-test 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v valid t bsis2 t bsih2 inputs 80960HA/hd/ht advance information datasheet 43 figure 22. rise and fall time derating at 85c and minimum v cc figure 23. i cc active (power supply) vs. frequency 50pf 100pf 150pf time (ns) c l (pf) 5 4 3 2 1 2.0 to 0.8 v 0.8 to 2.0 v 0 i cc active (power supply) (ma) clkin frequency (mhz) 200 1800 1600 1400 1200 1000 800 600 400 10 20 30 40 ha ht hd 0 80960HA/hd/ht 44 advance information datasheet figure 24. i cc active (thermal) vs. frequency figure 25. output delay or hold vs. load capacitance i cc active (thermal) (ma) clkin frequency (mhz) 200 1400 1200 1000 800 600 400 10 20 30 40 ha ht hd 50 100 150 c l (pf) nom + 10 nom + 5 nom output valid delays (ns) @ 1.5 v 5.5 v input signals 3.3 v input signals 80960HA/hd/ht advance information datasheet 45 figure 26. output delay vs. temperature figure 27. output hold times vs. temperature figure 28. output delay vs. v cc nom - 0.0 nom - 0.4 nom - 0.5 output valid delays (ns) @ 1.5 v nom - 0.3 nom - 0.2 nom - 0.1 processor case temperature (c) 85c 0c nom + 0.5 nom + 0.1 nom + 0 output hold times (ns) @ 1.5 v nom + 0.2 nom + 0.3 nom + 0.4 processor case temperature (c) 85c 0c nom + 0.5 -nom + 0.3 -nom + 0.5 output valid or hold delays (ns) @ 1.5 v -nom + 0.1 nom + 0.1 nom + 0.3 v cc (volts) 3.15 3.45 80960HA/hd/ht 46 advance information datasheet 5.0 bus waveforms figure 29. cold reset waveform clkin ct3:0, ads , w/r ,dt/r , d31:0, stest reset v cc, vcc5, lock ,wait , den , blast breq, fail , dp3:0 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ invalid valid ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ inputs tsetup 1clkin thold 1clkin ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ a31:2, sup d/c , be3:0 b a b a ~ ~ ~ ~ ~ ~ once note: v cc stable: as specified in table20v diff specification for dual power supply requirements (3.3 v, 5 v) on page 30 reset high to first bus activity, ha=67, hd=34, ht=23 clkin periods clkin and v cc stable to reset high, minimum 10,000 clkin periods for pll stabilization. bstall 80960HA/hd/ht advance information datasheet 47 figure 30. warm reset waveform ~ ~ ~ ~ ~ ~ ~ ~ maximum reset low to reset state 16 clkin periods 1clkin ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clkin ads , dt/r sup , d31:0, stest reset lock ,wait , den ,blast , a31:2, d/c ,be3:0 dp3:0 valid ~ ~ ~ ~ thold tsetup 1clkin ~ ~ ~ ~ w/r ,breq ,fail, ~ ~ ~ ~ bstall minimum reset low time 16 clkin periods reset high to first bus activity, ha=67, hd=34, ht=23 clkin periods 80960HA/hd/ht 48 advance information datasheet figure 31. entering once mode clkin ads ,be3:0 , a31:2, reset once ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ clkin and v cc stable and reset low and once low to reset high, minimum 10,000 clkin periods. d31:0, lock ,wait , blast ,w/r ,d/c ,den , dt/r ,holda, ct3:0, bstall, dp3:0, pchk blast ,fail ,sup ,breq, v cc, vcc5 ~ ~ ~ ~ ~ ~ ~ ~ oncemodeisenteredwithin1clkin period after once becomes low while reset is low. ~ ~ ~ ~ ~ ~ ~ ~ clkin may neither float nor remain idle. it must continue to run. notes: 1. once mode may be entered prior to the rising edge of reset : once input is not latched until the rising edge of reset . 2. the once input may be removed after the processor enters once mode. 80960HA/hd/ht advance information datasheet 49 figure 32. non-burst, non-pipelined requests without wait states in ads a31:2, sup , d/c , lock, ct3:0 w/r blast dt/r den wait d31:0, clkin ad ad ad in valid valid valid burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 disabled 0 off 0 0 0000 x xx x x enabled 1 0 00 0 00000 0 00 disabled 0 0 00000 out function bit value be3:0 , dp3:0 pchk external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. pmcon 80960HA/hd/ht 50 advance information datasheet figure 33. non-burst, non-pipelined read request with wait states ads a31:2, be3:0 w/r blast dt/r den wait d31:0, clkin a 3 21 d1 in valid valid a dp3:0 pchk note: bits 31-30, 27-25, 13, and 5 are reserved. burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 disabled 0 off 0 1 0001 x xx x x enabled 1 x xx x xxxxx x xx disabled 0 3 00011 function bit value external ready control pipe- lining parity enable n rad pmcon d/c ,sup, lock ,ct3:0 80960HA/hd/ht advance information datasheet 51 figure 34. non-burst, non-pipelined write request with wait states ads a31:2, w/r blast dt/r den wait d31:0, clkin a3 2 1 d1 out a valid valid be3:0 dp3:0 pchk burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 disabled 0 off 0 1 0001 x xx x x enabled 1 x xxxxx 3 00011 x xx disabled 0 x xxxxx function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. pmcon d/c ,sup, lock ,ct3:0 80960HA/hd/ht 52 advance information datasheet figure 35. burst, non-pipelined read request without wait states, 32-bit bus in0 ads a31:4, sup, ct3:0,d/c , be3:0 ,lock w/r blast dt/r den a3:2 wait d31:0, clkin ad dd da in3 in2 in1 valid 00 01 10 11 dp3:0 pchk burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 off 0 0 0000 32-bit 10 x x enabled 1 x xx x xxxxx 0 00 disabled 0 0 00000 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. pmcon 80960HA/hd/ht advance information datasheet 53 figure 36. burst, non-pipelined read request with wait states, 32-bit bus ads a31:4, sup, ct3:0, d/c , be3:0 ,lock w/r blast dt/r den a3:2 wait d31:0, clkin a2 1 d 1 d 1 d 1d 1 a in1 in2 in3 in0 valid 00 11 01 10 dp3:0 pchk burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 off 0 1 0001 32-bit 10 x x enabled 1 x xx x xxxxx 1 01 disabled 0 2 00010 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. pmcon 80960HA/hd/ht 54 advance information datasheet figure 37. burst, non-pipelined write request without wait states, 32-bit bus ads a31:4, sup , ct3:0, d/c , be3:0 ,lock w/r blast dt/r den a3:2 wait d31:0, clkin ad dd da 00 01 10 11 out0 out3 out2 dp3:0 pchk out1 burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 off 0 0 0000 32-bit 10 x x enabled 1 0 00 0 00000 x xx disabled 0 x xxxxx function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. pmcon valid 80960HA/hd/ht advance information datasheet 55 figure 38. burst, non-pipelined write request with wait states, 32-bit bus ads a31:4, sup , ct3:0, d/c , be3:0 ,lock w/r blast dt/r den a3:2 wait d31:0, clkin a2 1 d 1 d 1 d 1d 1 a out0 valid 00 11 01 10 out1 out2 out3 dp3:0 pchk burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 off 32-bit 0 1 0001 10 x x enabled 1 1 01 2 00010 x xx disabled 0 x xxxxx function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. pmcon 80960HA/hd/ht 56 advance information datasheet figure 39. burst, non-pipelined read request with wait states, 16-bit bus ads sup ,ct3:0, w/r blast dt/r den a3:2 wait d31:0, clkin a2 1 d 1 d 1 d 1d 1 a valid a3:2 = 00 or 10 a3:2 = 01 or 11 d15:0 a1=0 d15:0 a1=1 d15:0 a1=0 d15:0 a1=1 d/c ,lock , a31:4, be3 /bhe, be1 /a1 be0 /ble dp3:0 pchk burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 off 0 1 0001 16-bit x x enabled 1 x xx x xxxxx 1 01 disabled 0 2 00010 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. 01 pmcon 80960HA/hd/ht advance information datasheet 57 figure 40. burst, non-pipelined read request with wait states, 8-bit bus ads sup ,ct3:0, w/r blast dt/r den a3:2 wait d31:0, clkin a2 1 d 1 d 1 d 1d 1 a valid a3:2 = 00, 01, 10 or 11 d7:0 byte 0 d7:0 byte 1 d7:0 byte 2 d7:0 byte 3 d/c ,lock , a31:4 be1 /a1, a1:0 = 00 a1:0 = 01 a1:0 = 10 a1:0 =11 be0 /a0 dp3:0 pchk burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 off 0 1 0001 8-bit x x enabled 1 x xx x xxxxx 1 01 disabled 0 2 00010 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. 00 pmcon 80960HA/hd/ht 58 advance information datasheet figure 41. non-burst, pipelined read request without wait states, 32-bit bus ads a31:4, sup, ct3:0, d/c , lock blast wait d31:0, clkin in d in d' in d'' in d''' in d'''' a a' d a'' d' a''' d'' a'''' d''' d'''' valid valid valid valid valid invalid dt/r den a3:2 be3:0 valid valid valid valid valid invalid w/r dp3:0 pchk 1. non-pipelined request concludes, pipelined reads begin. 2. pipelined reads conclude, non-pipelined requests begin. 1 2 burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 disabled 0 on 1 x xxxx 32-bit x x enabled 1 x xx x xxxxx x xx x x 0 00000 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. 10 invalid pmcon 80960HA/hd/ht advance information datasheet 59 figure 42. non-burst, pipelined read request with wait states, 32-bit bus ads a31:4, sup , ct3:0, d/c , w/r blast dt/r den a3:2 wait d31:0, clkin be3:0 a1 a' d 1 d ' in d' valid valid invalid in d lock valid valid invalid dp3:0 1. non-pipelined request concludes, pipelined reads begin 2. pipelined reads conclude, non-pipelined requests begin pchk 2 1 burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 disabled 0 on 1 x xxxx 32-bit x x enabled 1 x xx x xxxxx x xx x x 1 00001 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. 10 invalid pmcon 80960HA/hd/ht 60 advance information datasheet figure 43. burst, pipelined read request without wait states, 32-bit bus ads a31:4, sup, ct3:0, d/c , be3:0 ,lock w/r blast dt/r den a3:2 wait d31:0, clkin ad dda' d' d' valid valid in- valid valid 01 10 11 00 in d in d in d in d in d in d valid d in- valid dp3:0 pchk 1 2 burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 on 1 x xxxx 32-bit x x enabled 1 x xx x xxxxx 0 00 x x 0 00000 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. 10 pmcon 1. non-pipelined request concludes, pipelined reads begin 2. pipelined reads conclude, non-pipelined requests begin 80960HA/hd/ht advance information datasheet 61 figure 44. burst, pipelined read request with wait states, 32-bit bus ads a31:4, sup, ct3:0, d/c , be3:0 ,lock w/r a3:2 d31:0, wait blast dt/r den clkin in d in d in d in d in d' a 21 d 1d1d1 a' 21 valid d d' valid in- valid in- valid 00 01 10 11 valid in- valid dp3:0 pchk 1. non-pipelined request concludes, pipelined reads begin. 2. pipelined reads conclude, non-pipelined requests begin. 2 1 note: bits 31-30, 27-25, 13, and 5 are reserved. burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 on 1 x xxxx 32-bit x x enabled 1 x xx x xxxxx 1 01 x x 2 00010 function bit value external ready control pipe- lining parity enable n rad 10 pmcon 80960HA/hd/ht 62 advance information datasheet figure 45. burst, pipelined read request with wait states, 8-bit bus ads a31:4, sup, ct3:0, d/c , lock w/r a3:2 be1 /a1, wait blast dt/r den clkin d7:0 byte 0 d7:0 byte 1 d7:0 byte 2 d7:0 byte 3 d7:0 d' a2 1 d 1 d 1 d 1 a' 21 d d' in- valid valid in- valid be0 /a0 d31:0, a3:2 = 00, 01, 10, or 11 valid in- valid a1:0 = 00 a1:0 = 01 a1:0 = 10 a1:0 = 11 valid valid in- valid dp3:0 1. non-pipelined request concludes, pipelined reads begin 2. pipelined reads conclude, non-pipelined requests begin pchk 2 burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 on 1 x xxxx 8-bit x x enabled 1 x xx x xxxxx 1 01 x x 2 00010 function bit value external ready control pipe- lining parity enable n rad 00 note: bits 31-30, 27-25, 13, and 5 are reserved. pmcon 1 80960HA/hd/ht advance information datasheet 63 figure 46. burst, pipelined read request with wait states, 16-bit bus ads a31:4, sup, ct3:0, d/c , be0 /blc , w/r a3:2 be1 /a1 wait blast dt/r den clkin d15:0 a1=0 d15:0 a1=1 d15:0 a1=0 d15:0 a1=1 d15:0 d' a2 1 d 1 d 1 d 1 a' 21 valid d d' valid in- valid in- valid a3:2 = 00 or 10 a3:2 = 01 or 11 valid in- valid valid in- valid be3/bhe, d31:0, lock dp3:0 pchk 2 1 burst bus width odd parity n xda n wdd n wad n rdd 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 enabled 1 on 1 x xxxx 16-bit x x enabled 1 x xx x xxxxx 1 01 x x 2 00010 function bit value external ready control pipe- lining parity enable n rad note: bits 31-30, 27-25, 13, and 5 are reserved. 01 pmcon 1. non-pipelined request concludes, pipelined reads begin 2. pipelined reads conclude, non-pipelined requests begin 80960HA/hd/ht 64 advance information datasheet figure 47. using external ready clkin ads a31:4, sup, dt/r den ready w/r ct3:0, d/c , blast bterm a3:2 wait d31:0, be3:0 ,lock d0 d1 d2 d3 d0 d1 d2 d3 00 01 10 11 00 01 10 11 valid valid quad-word read request n rad =0,n rdd =0,n xda =0 ready enabled quad-word write request n wad =1,n wdd =0,n wda =0 ready enabled dp3:0 pchk a1 d d d d 1 a 2 d1 d1 d 1 d note: pipelining must be disabled to use ready . 80960HA/hd/ht advance information datasheet 65 figure 48. terminating a burst with bterm clkin ads a31:4, sup, dt/r den ready w/r ct3:0, d/c , blast bterm a3:2 wait d31:0, be3:0 ,lock d0 d1 d2 d3 valid quad-word read request n rad =0,n rdd =0,n rda =0 ready enabled 00 01 10 11 note :ready adds memory access time to data transfers, whether or not the bus access is a burst access. bterm interrupts a bus access, whether or not the bus access has more data transfers pending. either the ready signal or the bterm signal terminates a bus access when the signal is asserted during the last (or only) data transfer of the bus access. see note dp3:0 pchk d1 ad1 d aa1d1 80960HA/hd/ht 66 advance information datasheet the processor can stall (bstall asserted) even with an empty bus queue (breq deasserted). depending on the instruction stream and memory wait states, the two signals can be separated by several clkin cycles. bus arbitration logic that logically ands bstall and breq will not correctly grant the bus to the processor in all stall cases, potentially degrading processor performance. do not logically and bstall and breq together in arbitration logic. instead, the simplest bus arbitration should logically or bstall and breq to determine the processors bus ownership requirements. more sophisticated arbitration should recognize the priority nature of these two signals. using a traffic light analogy, breq is a yellow light warning of a possible processor stall and bstall is a red light indicating a stall in progress. figure 49. breq and bstall operation clkin ads blast breq bstall 80960HA/hd/ht advance information datasheet 67 figure 50. boff functional timing. boff occurs during a burst or non-burst data cycle. ads blast ready boff a31:2, sup, dp3:0 & d31:0, boff may not be asserted boff may not be asserted boff may be asserted to suspend request begin request end request suspend request non-burst ct3:0, d/c, be3:0 ,wait, den ,dt/r (writes) burst resume request ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ note :ready /bterm must be enabled; n rad ,n rdd ,n wad ,n wdd =0 ~ ~ ~ ~ valid valid clkin pchk ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ad a may change boff mode regenerate ads 80960HA/hd/ht 68 advance information datasheet figure 51. hold functional timing word read request n rad =1, n xda =1 word read request n rad =0, n xda =0 hold state hold state clkin ads a31:2, sup, ct3:0, d/c, be3:0 ,wait, den ,dt/r blast hold holda valid valid lock 80960HA/hd/ht advance information datasheet 69 figure 52. lock delays holda timing figure 53. fail functional timing clkin ads blast hold holda lock w/r reset fail 257,517 cycles 30 cycles 113 cycles (bus test) pass (internal self-test) pass ~ ~ ~ ~ ~ ~ ~ ~ fail fail 80960HA: 80960hd: 128,761 cycles 15 cycles 94 cycles 80960ht: 85,840 cycles 10 cycles 90 cycles 80960HA/hd/ht 70 advance information datasheet figure 54. a summary of aligned and unaligned transfers for 32-bit regions 04 812162024 01 234 5 6 one double-word short-word load/store word load/store double-word load/store short requests (unaligned) short request (aligned) short request (aligned) byte, byte requests word request (aligned) trey, byte, requests short, short requests byte, trey, requests byte offset word offset one double-word burst (aligned) trey, byte, trey, byte, requests short, short, short, short requests byte, trey, byte, trey, requests word, word requests request (aligned) notes: 1. all requests that are less than a word in size and are cacheable will be promoted to a word to be cached. this causes adjacent requests to occur for full words to the same address. 80960HA/hd/ht advance information datasheet 71 figure 55. a summary of aligned and unaligned transfers for 32-bit regions (continued) 04 8 12162024 0 123456 triple-word load/store quad-word load/store word, word, word requests requests 4word requests byte offset word offset one three-word request (aligned) trey, byte, trey, byte, trey, byte requests short, short, short requests short, short, short, short byte, trey, byte, trey, byte, trey requests word, word, word requests one four-word request (aligned) trey, byte, trey, byte, trey, byte trey, byte requests 8 short requests byte, trey, byte, trey, byte, trey, byte, trey, requests requests word, word word, 4word notes: 1. all requests that are less than a word in size and are cacheable will be promoted to a word to be cached. this causes adjacent requests to occur for full words to the same address. 80960HA/hd/ht 72 advance information datasheet figure 56. a summary of aligned and unaligned transfers for 16-bit bus 04 812162024 01 234 5 6 byte offset word offset double word 16-bit bus triple word 16-bit bus quad word 16-bit bus short 16-bit bus word 16-bit bus short four short burst (byte, short, byte) *2 (short) *4 (byte, short, byte)*2 four short burst, two short burst (byte, short, byte) *3 (short) *6 (byte, short, byte) *3 (two short burst) *3 (two short burst) *3 (four short burst)*2 (byte, short, byte) *4 (short) *8 (two short burst)*4 (two short burst) *4 short byte, byte (byte, short, byte) *4 four short burst tw o s h o r t b u r s t byte, short, byte (short)*2 two short burst byte, short, byte byte, byte (two short burst)*2 80960HA/hd/ht advance information datasheet 73 figure 57. a summary of aligned and unaligned transfers for 8-bit bus 04 812162024 01 234 56 byte offset word offset short 8-bit bus word 8-bit bus triple word 8-bit bus double word 8-bit bus quad word 16-bit bus twobyteburst twobyteburst twobyteburst byte, byte four byte burst three byte burst, byte (two byte burst)*2 (four byte burst)*3 (two byte burst) *6 (four byte burst)*3 four byte burst (four byte burst) *2 (three byte burst, byte)*2 (four byte burst) *2 (two byte burst) *4 (four byte burst) *2 (three byte burst, byte)*3 (byte, three byte burst) *3 (four byte burst)*3 (four byte burst)*4 (two byte burst) *8 (four byte burst)*4 (four byte burst) *4 (three byte burst, byte)*4 (byte, three byte burst) *4 byte, three byte burst (byte, three byte burst) *2 80960HA/hd/ht 74 advance information datasheet figure 58. idle bus operation clkin ads a31:4, sup ,d/c , lock w/r blast dt/r den a3:2 wait d31:0 ready , bterm write request n wad =2, n xda =0 ready disabled idle bus (not in hold acknowledge state) read request n rad =2, n xda =0 ready disabled in out valid valid valid valid valid valid pchk valid valid be3:0 ,ct3:0 80960HA/hd/ht advance information datasheet 75 figure 59. bus states ti = idle th = hold ta = address td = data tb = boffed taw= address to data wait to = once ta tb td 1 taw 2 tr w 4 tdw 3 th ti to tdw= data to data wait tdw= data to address wait !boff and read and n rdd =0 read and n rdd >0or write and n wdd >0 boff w d cnt = 1 !boff and w a cnt = 1 w x cnt=1 and hold w x cnt > 1 boff !boff hold hold !hold note: 1. when the pmcon for the region has external ready control enabled, wait states are inserted as long as ready and bterm are de-asserted. when read pipelining is enabled, the ta state of the subsequent read access is concurrent with the last data cycle of the access. because external ready control is disabled for read pipelining, the address cycle occurs during blast . 2. w a cnt is decremented during t aw 3. w d cnt is decremented during t dw 4. w x cnt is decremented during t rw !hold and w x cnt=1 and !request !hold and w x cnt=1 and request !reset and !hold and request reset and once and reset w a cnt > 1 read and n rad >0or write and n wad >0 !boff and read and n rad =0or !boff and write and n wad =0 !boff and ready and !blast or !hold and blast and request and n xda =0 w d cnt > 1 key: !boff and and n xda =0 hold and blast !boff and !hold and n xda =0 blast and and !blast or !boff and write and n wdd = 0 and !blast or n xda >0 request= one or more requests in the bus queue. read= the current access is a read. write= the current access is a write. reset blast and boff and !request !once ready! !boff and bterm and !blast or !boff and 80960HA/hd/ht 76 advance information datasheet 5.1 80960hx boundary scan chain table 25. 80960hx boundary scan chain (sheet 1 of 4) # boundary scan cell cell type comment dp3 bidirectional dp2 bidirectional dp0 bidirectional dp1 bidirectional stest input failbar output enable for failbar, bstall and breq control oncebar input boffbar input d0 bidirectional d1 bidirectional d2 bidirectional d3 bidirectional d4 bidirectional d5 bidirectional d6 bidirectional d7 bidirectional enable for dp(3:0) and d(31:0) control d8 bidirectional d9 bidirectional d10 bidirectional d11 bidirectional d12 bidirectional d13 bidirectional d14 bidirectional d15 bidirectional d16 bidirectional d17 bidirectional d18 bidirectional d19 bidirectional d20 bidirectional notes: 1. cell#1 connects to tdo and cell #112 connects to tdi. 2. all outputs are three-state. 3. in output and bidirectional signals, a logical 1 on the enable signal enables the output. a logical 0 three-states the output. 80960HA/hd/ht advance information datasheet 77 d21 bidirectional d22 bidirectional d23 bidirectional d24 bidirectional d25 bidirectional d26 bidirectional d27 bidirectional d28 bidirectional d29 bidirectional d30 bidirectional d31 bidirectional btermbar input rdybar input appears as readybar in bsdl file. hold input holda output enable for holda control control adsbar output be3bar output appears as bebar(3:0) in bsdl file. be2bar output be1bar output be0bar output blastbar output denbar output wrrdbar output appears as wrbar in bsdl file. dtrbar output enable for dtrbar control waitbar output bstall output datacodbar output appears as dcbar in bsdl file. usersupbar output appears as supbar in bsdl file. enable for adsbar, bebar, blastbar, denbar, wrrdbar, waitbar, dcbar, supbar and lockbar, control table 25. 80960hx boundary scan chain (sheet 2 of 4) # boundary scan cell cell type comment notes: 1. cell#1 connects to tdo and cell #112 connects to tdi. 2. all outputs are three-state. 3. in output and bidirectional signals, a logical 1 on the enable signal enables the output. a logical 0 three-states the output. 80960HA/hd/ht 78 advance information datasheet lockbar output breq output a31 output a30 output a29 output a28 output a27 output a26 output a25 output a24 output a23 output a22 output a21 output a20 output a19 output a18 output a17 output a16 output enable for a(31:0) and ct(3:0) control a15 output a14 output a13 output a12 output a11 output a10 output a9 output a8 output a7 output a6 output a5 output a4 output a3 output a2 output nmibar input table 25. 80960hx boundary scan chain (sheet 3 of 4) # boundary scan cell cell type comment notes: 1. cell#1 connects to tdo and cell #112 connects to tdi. 2. all outputs are three-state. 3. in output and bidirectional signals, a logical 1 on the enable signal enables the output. a logical 0 three-states the output. 80960HA/hd/ht advance information datasheet 79 xint7bar input appears as xintbar(7:0) in bsdl file. xint6bar input xint5bar input xint4bar input xint3bar input xint2bar input xint1bar input xint0bar input resetbar input clkin input ct3 output appears as ct(3:0) in bsdl file. ct2 output ct1 output ct0 output pchk output appears as pchkbar in bsdl file. pchk enable control table 25. 80960hx boundary scan chain (sheet 4 of 4) # boundary scan cell cell type comment notes: 1. cell#1 connects to tdo and cell #112 connects to tdi. 2. all outputs are three-state. 3. in output and bidirectional signals, a logical 1 on the enable signal enables the output. a logical 0 three-states the output. 80960HA/hd/ht 80 advance information datasheet 5.2 boundary scan description language example boundary-scan description language (bsdl) example 14-2 meets the de facto standard means of describing essential features of ansi/ieee 1149.1-1993 compliant devices. example 1. boundary-scan description language (bsdl) for pga package example (sheet 1 of 8) -- copyright intel corp. 1995 - - *************************************************************************** - - intel corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. - - *************************************************************************** - - boundary-scan description language (bsdl version 0.0) is a de-facto standard means of describing essential features of ansi/ieee 1149.1-1990 compliant devices. this language is under consideration by the ieee for formal inclusion within a supplement to the 1149.1-1990 standard. the generation of the supplement entails an extensive ieee review and a formal acceptance balloting procedure which may change the resultant form of the language. be aware that this process may extend well into 1993, and at this time the ieee does not endorse or hold an opinion on the language. - - *************************************************************************** -- -- i960(r) processor bsdl model 80960HA/hd/ht advance information datasheet 81 -- project code ha -- file **not** verified electrically -- ------------------------------------------------ -- rev 0.7 18 dec 1995 updated for a-1 stepping. -- rev 0.6 08 dec 1994 -- rev 0.5 21 nov 1994 -- rev 0.4 31 oct 1994 -- rev 0.3 26 july 1994 -- rev 0.2 22 june 1994 -- rev 0.1 16 mar 1994 -- rev 0.0 30 aug 1993 entity ha_processor is generic(physical_pin_map : string:= pga); port (a : out bit_vector(2 to 31); adsbar : out bit; bebar : out bit_vector(0 to 3); blastbar : out bit; boffbar : in bit; breq : out bit; bstall : out bit; btermbar : in bit; ct : out bit_vector(0 to 3); clkin : in bit; d : inout bit_vector(0 to 31); denbar : out bit; dp : inout bit_vector(0 to 3); dtrbar : out bit; dcbar : out bit; failbar : out bit; hold : in bit; holda : out bit; lockbar : out bit; nmibar : in bit; oncebar : in bit; pchkbar : out bit; readybar : in bit; resetbar : in bit; stest : in bit; example 1. boundary-scan description language (bsdl) for pga package example (sheet 2 of 8) 80960HA/hd/ht 82 advance information datasheet supbar : out bit; tck : in bit; tdi : in bit; tdo : out bit; tms : in bit; trst : in bit; waitbar : out bit; wrbar : out bit; xintbar : in bit_vector(0 to 7); fivevref : linkage bit; vccpll : linkage bit; voltdet : out bit; vcc1 : linkage bit_vector(0 to 23); vcc2 : linkage bit_vector(0 to 20); vss1 : linkage bit_vector(0 to 25); vss2 : linkage bit_vector(0 to 22); nc : linkage bit_vector(0 to 4) ); use std_1149_1_1990.all; use i960ha_a.all; attribute pin_map of ha_processor : entity is physical_pin_map; constant pga:pin_map_string := a : (d16, d17, e16, e17, f17, g16, g17, h17, j17,& k17, l17, l16, m17, n17, n16, p17, q17, p16,& p15, q16, r17, r16, q15, s17, r15, s16, q14, & r14, q13, s15), adsbar : r06,& bebar : (r09, s07, s06, s05),& blastbar : s08,& boffbar : b01,& breq : r13,& bstall : r12,& btermbar : r04,& ct : (a11, a12, a13, a14),& clkin : c13,& example 1. boundary-scan description language (bsdl) for pga package example (sheet 3 of 8) 80960HA/hd/ht advance information datasheet 83 d : (e03, c02, d02, c01, e02, d01, f02, e01, f01,& g01, h02, h01, j01, k01, l02, l01, m01, n01,& n02, p01, p02, q01, p03, q02, r01, s01, q03,& r02, q04, s02, q05, r03),& denbar : s09,& dp : (a03, b03, a04, b04),& dtrbar : s11,& dcbar : s13,& failbar : a02,& hold : r05,& holda : s04,& lockbar : s14,& nmibar : d15,& oncebar : c03,& pchkbar : b08,& readybar : s03,& resetbar : a16,& stest : b02,& supbar : q12,& tck : b05,& tdi : a07,& tdo : a08,& tms : b06,& trst : a06,& waitbar : s12,& wrbar : s10,& xintbar : (b15, a15, a17, b16, c15, b17, c16, c17),& fivevref : c05,& voltdet : a05,& vccpll : b10,& vcc1 : (m02, k02, j02, g02, n03, f03, c06, b07, b09, b11,& b12, c14, e15, f16, h16, j16, k16, m16, n15, q06,& r07, r08, r10, r11),& vss1 : (g03, h03, j03, k03, l03, m03, c07, c08, c09, c10,& c11, c12, q07, q08, q09, q10, q11, f15, g15, h15,& j15, k15, l15, m15, a01, c04),& nc : (a09, a10, b13, b14, d03); example 1. boundary-scan description language (bsdl) for pga package example (sheet 4 of 8) 80960HA/hd/ht 84 advance information datasheet attribute tap_scan_in of tdi : signal is true; attribute tap_scan_mode of tms : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_reset of trst : signal is true; attribute tap_scan_clock of tck : signal is (66.0e6, both); attribute instruction_length of ha_processor: entity is 4; attribute instruction_opcode of ha_processor: entity is bypass (1111), & extest (0000), & sample (0001), & idcode (0010), & rubist (0111), & clamp (0100), & highz (1000), & reserved (1011, 1100); attribute instruction_capture of ha_processor: entity is 0001; attribute instruction_private of ha_processor: entity is reserved ; attribute idcode_register of ha_processor: entity is 0010 & --version, 1000100001000000 & --part number 00000001001 & --manufacturers identity 1; --required by the standard attribute register_access of ha_processor: entity is runbist[32] (rubist), & bypass (clamp, highz); {***************************************************************************} { the first cell, cell 0, is closest to tdo } { bc_1:control, output3 cbsc_1:bidir bc_4: input, clock } {***************************************************************************} example 1. boundary-scan description language (bsdl) for pga package example (sheet 5 of 8) 80960HA/hd/ht advance information datasheet 85 attribute boundary_cells of ha_processor: entity is bc_4, bc_1, cbsc_1; attribute boundary_length of ha_processor: entity is 112; attribute boundary_register of ha_processor: entity is 0 (cbsc_1, dp(3), bidir, x, 17, 1, z), & 1 (cbsc_1, dp(2), bidir, x, 17, 1, z), & 2 (cbsc_1, dp(0), bidir, x, 17, 1, z), & 3 (cbsc_1, dp(1), bidir, x, 17, 1, z), & 4 (bc_4, stest, input, x), & 5 (bc_1, failbar, output3, x, 6, 1, z), & 6 (bc_1, *, control, 1), & 7 (bc_4, oncebar, input, x), & 8 (bc_4, boffbar, input, x), & 9 (cbsc_1, d(0), bidir, x, 17, 1, z), & 10 (cbsc_1, d(1), bidir, x, 17, 1, z), & 11 (cbsc_1, d(2), bidir, x, 17, 1, z), & 12 (cbsc_1, d(3), bidir, x, 17, 1, z), & 13 (cbsc_1, d(4), bidir, x, 17, 1, z), & 14 (cbsc_1, d(5), bidir, x, 17, 1, z), & 15 (cbsc_1, d(6), bidir, x, 17, 1, z), & 16 (cbsc_1, d(7), bidir, x, 17, 1, z), & 17 (bc_1, *, control, 1), & 18 (cbsc_1, d(8), bidir, x, 17, 1, z), & 19 (cbsc_1, d(9), bidir, x, 17, 1, z), & 20 (cbsc_1, d(10), bidir, x, 17, 1, z), & 21 (cbsc_1, d(11), bidir, x, 17, 1, z), & 22 (cbsc_1, d(12), bidir, x, 17, 1, z), & 23 (cbsc_1, d(13), bidir, x, 17, 1, z), & 24 (cbsc_1, d(14), bidir, x, 17, 1, z), & 25 (cbsc_1, d(15), bidir, x, 17, 1, z), & 26 (cbsc_1, d(16), bidir, x, 17, 1, z), & 27 (cbsc_1, d(17), bidir, x, 17, 1, z), & 28 (cbsc_1, d(18), bidir, x, 17, 1, z), & 29 (cbsc_1, d(19), bidir, x, 17, 1, z), & 30 (cbsc_1, d(20), bidir, x, 17, 1, z), & 31 (cbsc_1, d(21), bidir, x, 17, 1, z), & 32 (cbsc_1, d(22), bidir, x, 17, 1, z), & 33 (cbsc_1, d(23), bidir, x, 17, 1, z), & 34 (cbsc_1, d(24), bidir, x, 17, 1, z), & example 1. boundary-scan description language (bsdl) for pga package example (sheet 6 of 8) 80960HA/hd/ht 86 advance information datasheet 35 (cbsc_1, d(25), bidir, x, 17, 1, z), & 36 (cbsc_1, d(26), bidir, x, 17, 1, z), & 37 (cbsc_1, d(27), bidir, x, 17, 1, z), & 38 (cbsc_1, d(28), bidir, x, 17, 1, z), & 39 (cbsc_1, d(29), bidir, x, 17, 1, z), & 40 (cbsc_1, d(30), bidir, x, 17, 1, z), & 41 (cbsc_1, d(31), bidir, x, 17, 1, z), & 42 (bc_4, btermbar, input, x), & 43 (bc_4, readybar, input, x), & 44 (bc_4, hold, input, x), & 45 (bc_1, holda, output3, x, 46, 1, z), & 46 (bc_1, *, control, 1), & 47 (bc_1, adsbar, output3, x, 61, 1, z), & 48 (bc_1, bebar(3), output3, x, 61, 1, z), & 49 (bc_1, bebar(2), output3, x, 61, 1, z), & 50 (bc_1, bebar(1), output3, x, 61, 1, z), & 51 (bc_1, bebar(0), output3, x, 61, 1, z), & 52 (bc_1, blastbar, output3, x, 61, 1, z), & 53 (bc_1, denbar, output3, x, 61, 1, z), & 54 (bc_1, wrbar, output3, x, 61, 1, z), & 55 (bc_1, dtrbar, output3, x, 56, 1, z), & 56 (bc_1, *, control, 1), & 57 (bc_1, waitbar, output3, x, 61, 1, z), & 58 (bc_1, bstall, output3, x, 6, 1, z), & 59 (bc_1, dcbar, output3, x, 61, 1, z), & 60 (bc_1, supbar, output3, x, 61, 1, z), & 61 (bc_1, *, control, 1), & 62 (bc_1, lockbar, output3, x, 61, 1, z), & 63 (bc_1, breq, output3, x, 6, 1, z), & 64 (bc_1, a(31), output3, x, 80, 1, z), & 65 (bc_1, a(30), output3, x, 80, 1, z), & 66 (bc_1, a(29), output3, x, 80, 1, z), & 67 (bc_1, a(28), output3, x, 80, 1, z), & 68 (bc_1, a(27), output3, x, 80, 1, z), & 69 (bc_1, a(26), output3, x, 80, 1, z), & 70 (bc_1, a(25), output3, x, 80, 1, z), & 71 (bc_1, a(24), output3, x, 80, 1, z), & 72 (bc_1, a(23), output3, x, 80, 1, z), & 73 (bc_1, a(22), output3, x, 80, 1, z), & example 1. boundary-scan description language (bsdl) for pga package example (sheet 7 of 8) 80960HA/hd/ht advance information datasheet 87 74 (bc_1, a(21), output3, x, 80, 1, z), & 75 (bc_1, a(20), output3, x, 80, 1, z), & 76 (bc_1, a(19), output3, x, 80, 1, z), & 77 (bc_1, a(18), output3, x, 80, 1, z), & 78 (bc_1, a(17), output3, x, 80, 1, z), & 79 (bc_1, a(16), output3, x, 80, 1, z), & 80 (bc_1, *, control, 1), & 81 (bc_1, a(15), output3, x, 80, 1, z), & 82 (bc_1, a(14), output3, x, 80, 1, z), & 83 (bc_1, a(13), output3, x, 80, 1, z), & 84 (bc_1, a(12), output3, x, 80, 1, z), & 85 (bc_1, a(11), output3, x, 80, 1, z), & 86 (bc_1, a(10), output3, x, 80, 1, z), & 87 (bc_1, a(9), output3, x, 80, 1, z), & 88 (bc_1, a(8), output3, x, 80, 1, z), & 89 (bc_1, a(7), output3, x, 80, 1, z), & 90 (bc_1, a(6), output3, x, 80, 1, z), & 91 (bc_1, a(5), output3, x, 80, 1, z), & 92 (bc_1, a(4), output3, x, 80, 1, z), & 93 (bc_1, a(3), output3, x, 80, 1, z), & 94 (bc_1, a(2), output3, x, 80, 1, z), & 95 (bc_4, nmibar, input, x), & 96 (bc_4, xintbar(7), input, x), & 97 (bc_4, xintbar(6), input, x), & 98 (bc_4, xintbar(5), input, x), & 99 (bc_4, xintbar(4), input, x), & 100(bc_4, xintbar(3), input, x), & 101(bc_4, xintbar(2), input, x), & 102(bc_4, xintbar(1), input, x), & 103(bc_4, xintbar(0), input, x), & 104(bc_4, resetbar, input, x), & 105(bc_4, clkin, input, x), & 106(bc_1, ct(3), output3, x, 80, 1, z), & 107(bc_1, ct(2), output3, x, 80, 1, z), & 108(bc_1, ct(1), output3, x, 80, 1, z), & 109(bc_1, ct(0), output3, x, 80, 1, z), & 110(bc_1, pchkbar, output3, x, 111, 1, z), & 111(bc_1, *, control, 1); end ha_processor; example 1. boundary-scan description language (bsdl) for pga package example (sheet 8 of 8) 80960HA/hd/ht 88 advance information datasheet example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 1 of 8) -- copyright intel corporation 1995, 1996 -- ***************************************************************************** -- intel corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. -- ***************************************************************************** -- boundary-scan description language (bsdl version 0.0) is a de-facto -- standard means of describing essential features of ansi/ieee 1149.1-1990 compliant devices. this language is under consideration by the ieee for formal inclusion within a supplement to the 1149.1-1990 standard. the generation of the supplement entails an extensive ieee review and a formal acceptance balloting procedure which may change the resultant form of the language. be aware that this process may extend well into 1993, and at this time the ieee does not endorse or hold an opinion on the language. -- i960(r) processor bsdl model -- project code ha -- file **not** verified electrically -- ----------------------------------------------- -- rev 0.8 4 apr 1996 changed for pq2 package -- rev 0.7 18 dec 1995 updated for a-1 stepping. -- rev 0.6 08 dec 1994 -- rev 0.5 21 nov 1994 -- rev 0.4 31 oct 1994 -- rev 0.3 26 july 1994 -- rev 0.2 22 june 1994 -- rev 0.1 16 mar 1994 -- rev 0.0 30 aug 1993 80960HA/hd/ht advance information datasheet 89 entity ha_processor is generic(physical_pin_map : string:= pq2); port (a : out bit_vector(2 to 31); adsbar : out bit; bebar : out bit_vector(0 to 3); blastbar : out bit; boffbar : in bit; breq : out bit; bstall : out bit; btermbar : in bit; ct : out bit_vector(0 to 3); clkin : in bit; d : inout bit_vector(0 to 31); denbar : out bit; dp : inout bit_vector(0 to 3); dtrbar : out bit; dcbar : out bit; failbar : out bit; hold : in bit; holda : out bit; lockbar : out bit; nmibar : in bit; oncebar : in bit; pchkbar : out bit; readybar : in bit; resetbar : in bit; stest : in bit; supbar : out bit; tck : in bit; tdi : in bit; tdo : out bit; tms : in bit; trst : in bit; waitbar : out bit; wrbar : out bit; xintbar : in bit_vector(0 to 7); fivevref : linkage bit; vccpll : linkage bit; example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 2 of 8) 80960HA/hd/ht 90 advance information datasheet vcc1 : linkage bit_vector(0 to 23); vcc2 : linkage bit_vector(0 to 23); vss1 : linkage bit_vector(0 to 23); vss2 : linkage bit_vector(0 to 23) ); use std_1149_1_1990.all; use i960ha_a.all; attribute pin_map of ha_processor : entity is physical_pin_map; constant pq2:pin_map_string := a : (151, 150, 147, 146, 145, 144, 141, 140, 139, 138,& 135, 134, 133, 132, 127, 126, 125, 124, 121, 120,& 119, 118, 113, 112, 111, 110, 107, 106, 105, 104),& adsbar : 77,& bebar : (83, 82, 79, 78),& blastbar : 84,& boffbar : 10,& breq : 100,& bstall : 91,& btermbar : 67,& ct : (183, 182, 181, 180),& clkin : 175,& d : (12, 13, 14, 15, 20, 21, 22, 23, 26, 27, 28, 29,& 34, 35, 36, 37, 39, 40, 41, 42, 45, 50, 51, 52,& 54, 55, 56, 57, 61, 62, 63, 64),& denbar : 85,& dp : (206, 207, 203, 202),& dtrbar : 89,& dcbar : 96,& failbar : 5,& hold : 69,& holda : 72,& lockbar : 99,& nmibar : 159,& example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 3 of 8) 80960HA/hd/ht advance information datasheet 91 oncebar : 6,& pchkbar : 189,& readybar : 68,& resetbar : 174,& stest : 208,& supbar : 97,& tck : 194,& tdi : 191,& tdo : 188,& tms : 192,& trst : 193,& waitbar : 90,& wrbar : 88,& xintbar : (169, 168, 167, 166, 163, 162, 161, 160),& fivevref : 197,& vccpll : 177,& vcc1 : (1, 4, 9, 11, 17, 19, 25, 31, 33, 38, 44, 46,& 49, 59, 60, 66, 71, 74, 76, 81, 87, 92, 95, 101),& vcc2 : (102, 109, 115, 117, 123, 128, 131, 137, 143, 149,& 153, 154, 158, 165, 171, 173, 176, 179, 185, 187,& 196, 199, 201, 204),& vss1 : (2, 3, 7, 8, 16, 18, 24, 30, 32, 43, 47, 48,& 53, 58, 65, 70, 73, 75, 80, 86, 93, 94, 98, 103),& vss2 : (108, 114, 116, 122, 129, 130, 136, 142, 148, 152,& 155, 156, 157, 164, 170, 172, 178, 184, 186, 190,& 195, 198, 200, 205); attribute tap_scan_in of tdi : signal is true; attribute tap_scan_mode of tms : signal is true; attribute tap_scan_out of tdo : signal is true; attribute tap_scan_reset of trst : signal is true; attribute tap_scan_clock of tck : signal is (66.0e6, both); attribute instruction_length of ha_processor: entity is 4; attribute instruction_opcode of ha_processor: entity is example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 4 of 8) 80960HA/hd/ht 92 advance information datasheet bypass (1111), & extest (0000), & sample (0001), & idcode (0010), & rubist (0111), & clamp (0100), & highz (1000), & reserved (1011, 1100); attribute instruction_capture of ha_processor: entity is 0001; attribute instruction_private of ha_processor: entity is reserved ; attribute idcode_register of ha_processor: entity is 0001 & version, 1000100001000000 & part number 00000001001& manufacturers identity 1; required by the standard attribute register_access of ha_processor: entity is runbist[32] (rubist), & bypass (clamp, highz); ******************************************************************************* { the first cell, cell 0, is closest to tdo } { bc_1:control, output3 cbsc_1:bidir bc_4: input, clock } ******************************************************************************* attribute boundary_cells of ha_processor: entity is bc_4, bc_1, cbsc_1; attribute boundary_length of ha_processor: entity is 112; attribute boundary_register of ha_processor: entity is 0 (cbsc_1, dp(3), bidir, x, 17, 1, z), & 1 (cbsc_1, dp(2), bidir, x, 17, 1, z), & 2 (cbsc_1, dp(0), bidir, x, 17, 1, z), & 3 (cbsc_1, dp(1), bidir, x, 17, 1, z), & 4 (bc_4, stest, input, x), & 5 (bc_1, failbar, output3, x, 6, 1, z), & example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 5 of 8) 80960HA/hd/ht advance information datasheet 93 6 (bc_1, *, control, 1), & 7 (bc_4, oncebar, input, x), & 8 (bc_4, boffbar, input, x), & 9 (cbsc_1, d(0), bidir, x, 17, 1, z), & 10 (cbsc_1, d(1), bidir, x, 17, 1, z), & 11 (cbsc_1, d(2), bidir, x, 17, 1, z), & 12 (cbsc_1, d(3), bidir, x, 17, 1, z), & 13 (cbsc_1, d(4), bidir, x, 17, 1, z), & 14 (cbsc_1, d(5), bidir, x, 17, 1, z), & 15 (cbsc_1, d(6), bidir, x, 17, 1, z), & 16 (cbsc_1, d(7), bidir, x, 17, 1, z), & 17 (bc_1, *, control, 1), & 18 (cbsc_1, d(8), bidir, x, 17, 1, z), & 19 (cbsc_1, d(9), bidir, x, 17, 1, z), & 20 (cbsc_1, d(10), bidir, x, 17, 1, z), & 21 (cbsc_1, d(11), bidir, x, 17, 1, z), & 22 (cbsc_1, d(12), bidir, x, 17, 1, z), & 23 (cbsc_1, d(13), bidir, x, 17, 1, z), & 24 (cbsc_1, d(14), bidir, x, 17, 1, z), & 25 (cbsc_1, d(15), bidir, x, 17, 1, z), & 26 (cbsc_1, d(16), bidir, x, 17, 1, z), & 27 (cbsc_1, d(17), bidir, x, 17, 1, z), & 28 (cbsc_1, d(18), bidir, x, 17, 1, z), & 29 (cbsc_1, d(19), bidir, x, 17, 1, z), & 30 (cbsc_1, d(20), bidir, x, 17, 1, z), & 31 (cbsc_1, d(21), bidir, x, 17, 1, z), & 32 (cbsc_1, d(22), bidir, x, 17, 1, z), & 33 (cbsc_1, d(23), bidir, x, 17, 1, z), & 34 (cbsc_1, d(24), bidir, x, 17, 1, z), & 35 (cbsc_1, d(25), bidir, x, 17, 1, z), & 36 (cbsc_1, d(26), bidir, x, 17, 1, z), & 37 (cbsc_1, d(27), bidir, x, 17, 1, z), & 38 (cbsc_1, d(28), bidir, x, 17, 1, z), & 39 (cbsc_1, d(29), bidir, x, 17, 1, z), & 40 (cbsc_1, d(30), bidir, x, 17, 1, z), & example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 6 of 8) 80960HA/hd/ht 94 advance information datasheet 41 (cbsc_1, d(31), bidir, x, 17, 1, z), & 42 (bc_4, btermbar, input, x), & 43 (bc_4, readybar, input, x), & 44 (bc_4, hold, input, x), & 45 (bc_1, holda, output3, x, 46, 1, z), & 46 (bc_1, *, control, 1), & 47 (bc_1, adsbar, output3, x, 61, 1, z), & 48 (bc_1, bebar(3), output3, x, 61, 1, z), & 49 (bc_1, bebar(2), output3, x, 61, 1, z), & 50 (bc_1, bebar(1), output3, x, 61, 1, z), & 51 (bc_1, bebar(0), output3, x, 61, 1, z), & 52 (bc_1, blastbar, output3, x, 61, 1, z), & 53 (bc_1, denbar, output3, x, 61, 1, z), & 54 (bc_1, wrbar, output3, x, 61, 1, z), & 55 (bc_1, dtrbar, output3, x, 56, 1, z), & 56 (bc_1, *, control, 1), & 57 (bc_1, waitbar, output3, x, 61, 1, z), & 58 (bc_1, bstall, output3, x, 6, 1, z), & 59 (bc_1, dcbar, output3, x, 61, 1, z), & 60 (bc_1, supbar, output3, x, 61, 1, z), & 61 (bc_1, *, control, 1), & 62 (bc_1, lockbar, output3, x, 61, 1, z), & 63 (bc_1, breq, output3, x, 6, 1, z), & 64 (bc_1, a(31), output3, x, 80, 1, z), & 65 (bc_1, a(30), output3, x, 80, 1, z), & 66 (bc_1, a(29), output3, x, 80, 1, z), & 67 (bc_1, a(28), output3, x, 80, 1, z), & 68 (bc_1, a(27), output3, x, 80, 1, z), & 69 (bc_1, a(26), output3, x, 80, 1, z), & 70 (bc_1, a(25), output3, x, 80, 1, z), & 71 (bc_1, a(24), output3, x, 80, 1, z), & 72 (bc_1, a(23), output3, x, 80, 1, z), & 73 (bc_1, a(22), output3, x, 80, 1, z), & 74 (bc_1, a(21), output3, x, 80, 1, z), & 75 (bc_1, a(20), output3, x, 80, 1, z), & example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 7 of 8) 80960HA/hd/ht advance information datasheet 95 76 (bc_1, a(19), output3, x, 80, 1, z), & 77 (bc_1, a(18), output3, x, 80, 1, z), & 78 (bc_1, a(17), output3, x, 80, 1, z), & 79 (bc_1, a(16), output3, x, 80, 1, z), & 80 (bc_1, *, control, 1), & 81 (bc_1, a(15), output3, x, 80, 1, z), & 82 (bc_1, a(14), output3, x, 80, 1, z), & 83 (bc_1, a(13), output3, x, 80, 1, z), & 84 (bc_1, a(12), output3, x, 80, 1, z), & 85 (bc_1, a(11), output3, x, 80, 1, z), & 86 (bc_1, a(10), output3, x, 80, 1, z), & 87 (bc_1, a(9), output3, x, 80, 1, z), & 88 (bc_1, a(8), output3, x, 80, 1, z), & 89 (bc_1, a(7), output3, x, 80, 1, z), & 90 (bc_1, a(6), output3, x, 80, 1, z), & 91 (bc_1, a(5), output3, x, 80, 1, z), & 92 (bc_1, a(4), output3, x, 80, 1, z), & 93 (bc_1, a(3), output3, x, 80, 1, z), & 94 (bc_1, a(2), output3, x, 80, 1, z), & 95 (bc_4, nmibar, input, x), & 96 (bc_4, xintbar(7), input, x), & 97 (bc_4, xintbar(6), input, x), & 98 (bc_4, xintbar(5), input, x), & 99 (bc_4, xintbar(4), input, x), & 100(bc_4, xintbar(3), input, x), & 101(bc_4, xintbar(2), input, x), & 102(bc_4, xintbar(1), input, x), & 103(bc_4, xintbar(0), input, x), & 104(bc_4, resetbar, input, x), & 105(bc_4, clkin, input, x), & 106(bc_1, ct(3), output3, x, 80, 1, z), & 107(bc_1, ct(2), output3, x, 80, 1, z), & 108(bc_1, ct(1), output3, x, 80, 1, z), & 109(bc_1, ct(0), output3, x, 80, 1, z), & 110(bc_1, pchkbar, output3, x, 111,1, z), & 111(bc_1, *, control, 1); end ha_processor; example 2. boundary-scan description language (bsdl) for pq2 package example (sheet 8 of 8) 80960HA/hd/ht 96 advance information datasheet table 26. data sheet version -006 to -007 revision history section description entire data sheet formatted in new template. 32-bit parallel architecture on page 1 revised 1.2 gbyte internal bandwith (75 mhz) to 1.28 gbyte ... (80 mhz). copyright page updated legal text. section 3.0, package information on page 6 added paaragraph two and ta b l e 5 . table 7 80960hx processor family pin descriptions on page 8 corrected minor typeset and spacing errors. breq ; revised description. once ; last sentence, changed low to high. tdi and tms ; removed last sentence, pull this pin low when not in use. figure 2 80960hx 168-pin pga pinout view from top (pins facing down) on page 12 added insert package marking diagram. figure 4 80960hx 208-pin pq4 pinout on page 18 added insert package marking diagram. table 10 80960hx pq4 pinout signal name order on page 19 corrected tdo (o was zero) and revised alphabetical ordering. table 11 80960hx pq4 pinout pin number order on page 21 corrected tdo (o was zero) and revised alphabetical ordering. section 4.1, absolute maximum ratings on page 29 revised v cc to vcc5 for voltage on other pins .... section 4.5, vccpll pin requirements on page 31 added section. table 21 80960hx dc characteristics on page 32 added footnote (1) to i lo notes column for tdo pin. added footnote (10) to c in ,c out and c i/o pin. table 22 80960hx ac characteristics on page 34 added overbars where required. modified t dvnh to list separate specifications for 3.3 v and 5 v. modified t ov2 ,t oh2 and t tvel to reflect specific 80960HA, 80960hd and 80960ht values. figure23i cc active (power supply) vs. frequency on page 43 changed 5 to 0 on clkin frequency axis. figure 49 breq and bstall operation on page 66 added figure and following text. |
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